Move to a model with a unified request object.

Constructor takes a bool to signify that it is either a cpu_request or not a cpu_request.
When accedding variables of a cpu_request it asserts that it is a cpu_request.
It also asserts that a value being read has been written at some point in time prior (not gaurnteeing it is up to date, but it was at least written before read).

There is also a isCpuReq() function to determine if this is a cpu_request.  It should be called before accesing a cpu_request only variable.

SConscript:
    Add compilation support for request.cc
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/io_device.cc:
mem/page_table.cc:
mem/page_table.hh:
mem/port.cc:
    Update for unified request object and accessor functions.
mem/request.hh:
    Remove CpuRequest, make it a unified object.  Make variables private with accessor functions.

    May want to move things from .cc file into header (usually a assert() and either returning a value, or writting two).

--HG--
extra : convert_revision : f1e45cc490dadc7a418634539b03c3e72684a6e3

1 files changed, 9 insertions, 9 deletions

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index c74feec68..eb5d712b9 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -241,17 +241,17 @@ class CPUExecContext
     int getInstAsid() { return regs.instAsid(); }
     int getDataAsid() { return regs.dataAsid(); }
 
-    Fault translateInstReq(CpuRequestPtr &req)
+    Fault translateInstReq(RequestPtr &req)
     {
         return itb->translate(req, proxy);
     }
 
-    Fault translateDataReadReq(CpuRequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req)
     {
         return dtb->translate(req, proxy, false);
     }
 
-    Fault translateDataWriteReq(CpuRequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req)
     {
         return dtb->translate(req, proxy, true);
     }
@@ -273,17 +273,17 @@ class CPUExecContext
     int getInstAsid() { return asid; }
     int getDataAsid() { return asid; }
 
-    Fault translateInstReq(CpuRequestPtr &req)
+    Fault translateInstReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
 
-    Fault translateDataReadReq(CpuRequestPtr &req)
+    Fault translateDataReadReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
 
-    Fault translateDataWriteReq(CpuRequestPtr &req)
+    Fault translateDataWriteReq(RequestPtr &req)
     {
         return process->pTable->translate(req);
     }
@@ -292,7 +292,7 @@ class CPUExecContext
 
 /*
     template <class T>
-    Fault read(CpuRequestPtr &req, T &data)
+    Fault read(RequestPtr &req, T &data)
     {
 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
@@ -308,7 +308,7 @@ class CPUExecContext
     }
 
     template <class T>
-    Fault write(CpuRequestPtr &req, T &data)
+    Fault write(RequestPtr &req, T &data)
     {
 #if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
@@ -369,7 +369,7 @@ class CPUExecContext
         inst = new_inst;
     }
 
-    Fault instRead(CpuRequestPtr &req)
+    Fault instRead(RequestPtr &req)
     {
         panic("instRead not implemented");
         // return funcPhysMem->read(req, inst);