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authorAli Saidi <saidi@eecs.umich.edu>2006-03-30 15:59:49 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-30 15:59:49 -0500
commite196d20d9d047a869e1d853fd02077b1d909a576 (patch)
tree3b45bd223ff1d144af5f94fc9431f01b8a0bad61 /cpu/cpu_exec_context.hh
parent0b2deb2a8897fa857d2b3e1936401c6666fdc728 (diff)
downloadgem5-e196d20d9d047a869e1d853fd02077b1d909a576.tar.xz
Make TranslatingPort be a type of Port rather than something special
arch/alpha/arguments.cc: rather than returning 0, put a panic in... it will actually make us fix this rather than scratching our respective heads base/loader/object_file.cc: base/loader/object_file.hh: Object loader now takes a port rather than a translating port cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: sim/process.cc: Make translating port a type of port rather than anything special cpu/simple/cpu.cc: no need to grab a port from the cpu anymore mem/physical.cc: add an additional type of port to physicalmemory called "functional" Only used for functional accesses (loading binaries/syscall emu) mem/port.hh: make readBlok/writeBlob virtual so translating port can do the translation first mem/translating_port.cc: mem/translating_port.hh: Make TranslatingPort inherit from Port sim/system.cc: header file that doesn't exit removed --HG-- extra : convert_revision : 89b08f6146bba61f5605678d736055feab2fe6f7
Diffstat (limited to 'cpu/cpu_exec_context.hh')
-rw-r--r--cpu/cpu_exec_context.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 83afb3b85..9bf548a45 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -206,7 +206,7 @@ class CPUExecContext
AlphaITB *_itb, AlphaDTB *_dtb);
#else
CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process,
- int _asid, Port *mem_port);
+ int _asid);
// Constructor to use XC to pass reg file around. Not used for anything
// else.
CPUExecContext(RegFile *regFile);