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author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-14 16:08:32 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-14 16:08:32 -0500 |
commit | fa763d2ecfae16e84a9f9d689d19f746d84d08e3 (patch) | |
tree | 52474edfd8d1ab010a376b1eb66f4d9990fe4a54 /cpu/cpu_exec_context.hh | |
parent | f045b110cf1db6f9fc70589532b48d9cca339897 (diff) | |
parent | efe46430fac2419a02062e3b282324498a55df28 (diff) | |
download | gem5-fa763d2ecfae16e84a9f9d689d19f746d84d08e3.tar.xz |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
cpu/cpu_exec_context.cc:
Hand merge
--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
Diffstat (limited to 'cpu/cpu_exec_context.hh')
-rw-r--r-- | cpu/cpu_exec_context.hh | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 9268f6f3d..236619752 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -71,6 +71,8 @@ class CPUExecContext typedef TheISA::MachInst MachInst; typedef TheISA::MiscRegFile MiscRegFile; typedef TheISA::MiscReg MiscReg; + typedef TheISA::FloatReg FloatReg; + typedef TheISA::FloatRegBits FloatRegBits; public: typedef ExecContext::Status Status; @@ -375,19 +377,24 @@ class CPUExecContext return regs.intRegFile[reg_idx]; } - float readFloatRegSingle(int reg_idx) + FloatReg readFloatReg(int reg_idx, int width) { - return (float)regs.floatRegFile.d[reg_idx]; + return regs.floatRegFile.readReg(reg_idx, width); } - double readFloatRegDouble(int reg_idx) + FloatReg readFloatReg(int reg_idx) { - return regs.floatRegFile.d[reg_idx]; + return regs.floatRegFile.readReg(reg_idx); } - uint64_t readFloatRegInt(int reg_idx) + FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.floatRegFile.q[reg_idx]; + return regs.floatRegFile.readRegBits(reg_idx, width); + } + + FloatRegBits readFloatRegBits(int reg_idx) + { + return regs.floatRegFile.readRegBits(reg_idx); } void setIntReg(int reg_idx, uint64_t val) @@ -395,19 +402,24 @@ class CPUExecContext regs.intRegFile[reg_idx] = val; } - void setFloatRegSingle(int reg_idx, float val) + void setFloatReg(int reg_idx, FloatReg val, int width) + { + regs.floatRegFile.setReg(reg_idx, val, width); + } + + void setFloatReg(int reg_idx, FloatReg val) { - regs.floatRegFile.d[reg_idx] = (double)val; + regs.floatRegFile.setReg(reg_idx, val); } - void setFloatRegDouble(int reg_idx, double val) + void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.floatRegFile.d[reg_idx] = val; + regs.floatRegFile.setRegBits(reg_idx, val, width); } - void setFloatRegInt(int reg_idx, uint64_t val) + void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.floatRegFile.q[reg_idx] = val; + regs.floatRegFile.setRegBits(reg_idx, val); } uint64_t readPC() |