Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781

1 files changed, 8 insertions, 9 deletions

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 236619752..7ceb7f2d8 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -121,9 +121,6 @@ class CPUExecContext
 
     System *system;
 
-    /// Port that syscalls can use to access memory (provides translation step).
-    TranslatingPort *port;
-//    Memory *mem;
 
 #if FULL_SYSTEM
     AlphaITB *itb;
@@ -167,6 +164,9 @@ class CPUExecContext
     void profileSample();
 
 #else
+    /// Port that syscalls can use to access memory (provides translation step).
+    TranslatingPort *port;
+
     Process *process;
 
     // Address space ID.  Note that this is used for TIMING cache
@@ -203,9 +203,10 @@ class CPUExecContext
     // constructor: initialize context from given process structure
 #if FULL_SYSTEM
     CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
-                   AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
+                   AlphaITB *_itb, AlphaDTB *_dtb);
 #else
-    CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, Port *mem_port);
+    CPUExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid,
+            MemObject *memobj);
     // Constructor to use XC to pass reg file around.  Not used for anything
     // else.
     CPUExecContext(RegFile *regFile);
@@ -219,8 +220,6 @@ class CPUExecContext
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
 
-    TranslatingPort *getMemPort() { return port; }
-
     BaseCPU *getCpuPtr() { return cpu; }
 
     ExecContext *getProxy() { return proxy; }
@@ -230,8 +229,6 @@ class CPUExecContext
 #if FULL_SYSTEM
     System *getSystemPtr() { return system; }
 
-    PhysicalMemory *getPhysMemPtr() { return physmem; }
-
     AlphaITB *getITBPtr() { return itb; }
 
     AlphaDTB *getDTBPtr() { return dtb; }
@@ -255,6 +252,8 @@ class CPUExecContext
     }
 
 #else
+    TranslatingPort *getMemPort() { return port; }
+
     Process *getProcessPtr() { return process; }
 
     int getInstAsid() { return asid; }