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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2004-02-02 10:47:21 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2004-02-02 10:47:21 -0800 |
| commit | 7b07b0877f05cffa93b782a76a15791c1126216a (patch) | |
| tree | 9bc0cfd05f4f8bb0de7560c46e7bc144900e44e9 /cpu/exec_context.hh | |
| parent | 7c8413db101e1f0c92b10aab7130b34fe888391d (diff) | |
| download | gem5-7b07b0877f05cffa93b782a76a15791c1126216a.tar.xz | |
Change MemReqPtr parameters to references.
This avoids incrementing and decrementing the MemReq
reference counters on every call and return.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/exec_context.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
dev/alpha_console.cc:
dev/alpha_console.hh:
Change MemReqPtr parameters to references.
--HG--
extra : convert_revision : 3ba18bdd9f996563988402576bfdd3430e1ab1e5
Diffstat (limited to 'cpu/exec_context.hh')
| -rw-r--r-- | cpu/exec_context.hh | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f3c4b8015..b49db9720 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -189,17 +189,17 @@ class ExecContext int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -214,7 +214,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault dummyTranslation(MemReqPtr req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -225,15 +225,15 @@ class ExecContext req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return No_Fault; } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -241,7 +241,7 @@ class ExecContext #endif template <class T> - Fault read(MemReqPtr req, T& data) + Fault read(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) if (req->flags & LOCKED) { @@ -254,7 +254,7 @@ class ExecContext } template <class T> - Fault write(MemReqPtr req, T& data) + Fault write(MemReqPtr &req, T& data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) |