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| author | Nathan Binkert <binkertn@umich.edu> | 2004-02-03 11:24:03 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2004-02-03 11:24:03 -0500 |
| commit | 85bc028185830fb534c10c244d5f39fcfe8c4da6 (patch) | |
| tree | 59a830bc1aa9e0623cb997f20437925c300aff06 /cpu/exec_context.hh | |
| parent | 5164de4a03422090b253404a11b069d7d588c55e (diff) | |
| parent | 368e6e3e570430b207b0194290242a2f98e565ca (diff) | |
| download | gem5-85bc028185830fb534c10c244d5f39fcfe8c4da6.tar.xz | |
merge
--HG--
extra : convert_revision : 47425264e672f727cbb13aa7b9bb2a67790b25e8
Diffstat (limited to 'cpu/exec_context.hh')
| -rw-r--r-- | cpu/exec_context.hh | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index f3c4b8015..e9dc5efec 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -158,7 +158,7 @@ class ExecContext * number of executed instructions, for matching with syscall trace * points in EIO files. */ - Counter func_exe_insn; + Counter func_exe_inst; // // Count failed store conditionals so we can warn of apparent @@ -189,17 +189,17 @@ class ExecContext int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); } int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -214,7 +214,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault dummyTranslation(MemReqPtr req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -225,15 +225,15 @@ class ExecContext req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return No_Fault; } - Fault translateInstReq(MemReqPtr req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataReadReq(MemReqPtr req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault translateDataWriteReq(MemReqPtr req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -241,7 +241,7 @@ class ExecContext #endif template <class T> - Fault read(MemReqPtr req, T& data) + Fault read(MemReqPtr &req, T &data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) if (req->flags & LOCKED) { @@ -254,7 +254,7 @@ class ExecContext } template <class T> - Fault write(MemReqPtr req, T& data) + Fault write(MemReqPtr &req, T &data) { #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM) |