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author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
commit | 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d (patch) | |
tree | aa785d4b846823e1960c7b308e6de1c90cf6fb3f /cpu/exec_context.hh | |
parent | 3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff) | |
download | gem5-8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d.tar.xz |
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
Diffstat (limited to 'cpu/exec_context.hh')
-rw-r--r-- | cpu/exec_context.hh | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh index 3fa7d078e..3e0d77254 100644 --- a/cpu/exec_context.hh +++ b/cpu/exec_context.hh @@ -213,17 +213,17 @@ class ExecContext int getInstAsid() { return regs.instAsid(); } int getDataAsid() { return regs.dataAsid(); } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return itb->translate(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dtb->translate(req, false); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dtb->translate(req, true); } @@ -238,7 +238,7 @@ class ExecContext int getInstAsid() { return asid; } int getDataAsid() { return asid; } - Fault * dummyTranslation(MemReqPtr &req) + Fault dummyTranslation(MemReqPtr &req) { #if 0 assert((req->vaddr >> 48 & 0xffff) == 0); @@ -249,15 +249,15 @@ class ExecContext req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16; return NoFault; } - Fault * translateInstReq(MemReqPtr &req) + Fault translateInstReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataReadReq(MemReqPtr &req) + Fault translateDataReadReq(MemReqPtr &req) { return dummyTranslation(req); } - Fault * translateDataWriteReq(MemReqPtr &req) + Fault translateDataWriteReq(MemReqPtr &req) { return dummyTranslation(req); } @@ -265,7 +265,7 @@ class ExecContext #endif template <class T> - Fault * read(MemReqPtr &req, T &data) + Fault read(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) if (req->flags & LOCKED) { @@ -275,14 +275,14 @@ class ExecContext } #endif - Fault * error; + Fault error; error = mem->read(req, data); data = LittleEndianGuest::gtoh(data); return error; } template <class T> - Fault * write(MemReqPtr &req, T &data) + Fault write(MemReqPtr &req, T &data) { #if FULL_SYSTEM && defined(TARGET_ALPHA) @@ -340,7 +340,7 @@ class ExecContext inst = new_inst; } - Fault * instRead(MemReqPtr &req) + Fault instRead(MemReqPtr &req) { return mem->read(req, inst); } @@ -419,13 +419,13 @@ class ExecContext } #if FULL_SYSTEM - uint64_t readIpr(int idx, Fault * &fault); - Fault * setIpr(int idx, uint64_t val); + uint64_t readIpr(int idx, Fault &fault); + Fault setIpr(int idx, uint64_t val); int readIntrFlag() { return regs.intrflag; } void setIntrFlag(int val) { regs.intrflag = val; } - Fault * hwrei(); + Fault hwrei(); bool inPalMode() { return AlphaISA::PcPAL(regs.pc); } - void ev5_trap(Fault * fault); + void ev5_trap(Fault fault); bool simPalCheck(int palFunc); #endif @@ -435,7 +435,7 @@ class ExecContext * @todo How to do this properly so it's dependent upon ISA only? */ - void trap(Fault * fault); + void trap(Fault fault); #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) |