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authorRon Dreslinski <rdreslin@umich.edu>2006-04-07 18:16:11 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-04-07 18:16:11 -0400
commitae1a95ed9c9aa2b3c97272570575345dc3c37799 (patch)
tree2d83df1ac20e0fdff565d545844dd7cfc283c774 /cpu/exec_context.hh
parent2609ed2a7cf736834cafcf0b07465c45dfb567e3 (diff)
parent9e3d79694ca9e204bcbfa9c197db17b581dc7a29 (diff)
downloadgem5-ae1a95ed9c9aa2b3c97272570575345dc3c37799.tar.xz
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 85406b562373f7d768a44a8c327055cb02d3f6c5
Diffstat (limited to 'cpu/exec_context.hh')
-rw-r--r--cpu/exec_context.hh12
1 files changed, 6 insertions, 6 deletions
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index dd3d2cba1..9404b126b 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -152,11 +152,11 @@ class ExecContext
virtual int getInstAsid() = 0;
virtual int getDataAsid() = 0;
- virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateInstReq(RequestPtr &req) = 0;
- virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataReadReq(RequestPtr &req) = 0;
- virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
@@ -327,13 +327,13 @@ class ProxyExecContext : public ExecContext
int getInstAsid() { return actualXC->getInstAsid(); }
int getDataAsid() { return actualXC->getDataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{ return actualXC->translateInstReq(req); }
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{ return actualXC->translateDataReadReq(req); }
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{ return actualXC->translateDataWriteReq(req); }
// @todo: Do I need this?