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authorGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
commit0e4a80df1a471671b6ef7003e29124b6835ade42 (patch)
tree1d2c44d8c3462dd94c0fbf6e4f149e026c901aa8 /cpu/exetrace.hh
parenta48c24b61eedf580645ff0294b225d1e69a9444b (diff)
parent463aa6d49d49ba9c383f07207df57bad75c58ec9 (diff)
downloadgem5-0e4a80df1a471671b6ef7003e29124b6835ade42.tar.xz
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
Diffstat (limited to 'cpu/exetrace.hh')
-rw-r--r--cpu/exetrace.hh10
1 files changed, 6 insertions, 4 deletions
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 48d8966d8..d37c48ddd 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -46,13 +46,15 @@ namespace Trace {
class InstRecord : public Record
{
protected:
+ typedef TheISA::Addr Addr;
+ typedef TheISA::IntRegFile IntRegFile;
// The following fields are initialized by the constructor and
// thus guaranteed to be valid.
BaseCPU *cpu;
// need to make this ref-counted so it doesn't go away before we
// dump the record
- StaticInstPtr<TheISA> staticInst;
+ StaticInstPtr staticInst;
Addr PC;
bool misspeculating;
unsigned thread;
@@ -92,7 +94,7 @@ class InstRecord : public Record
public:
InstRecord(Tick _cycle, BaseCPU *_cpu,
- const StaticInstPtr<TheISA> &_staticInst,
+ const StaticInstPtr &_staticInst,
Addr _pc, bool spec, int _thread)
: Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
misspeculating(spec), thread(_thread)
@@ -169,8 +171,8 @@ InstRecord::setRegs(const IntRegFile &regs)
inline
InstRecord *
getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
- const StaticInstPtr<TheISA> staticInst,
- Addr pc, int thread = 0)
+ const StaticInstPtr staticInst,
+ TheISA::Addr pc, int thread = 0)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !xc->misspeculating())) {