Make changes so that coherence works on a timing bus for the top-level of caches.

This added a snoopResponse callback to the caches, and a NACK to requests.

cpu/memtest/memtest.cc:
    Modified to work with do_events:
    No multiple requests to the same block outstanding at the same time from the same tester
    Using false sharing, each tester does only 1 byte access using it's id as the blk offset
    Allow for cycles before signaling deadlock, with do events it can take time to complete (NACK/blocked bus)
cpu/memtest/memtest.hh:
    Updated to keep an id with each tester (used for address generation)
    Updated to keep a list of outstanding address to prevent multiple outstanding per tester
    //Should really look into doing store forwarding within the tester, then we can test more functionality

--HG--
extra : convert_revision : 05fbcf547e4ffab9d220aeb73126ed787ca82239

1 files changed, 10 insertions, 5 deletions

diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 72e0709d9..43b17a713 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -29,13 +29,14 @@
 #ifndef __MEMTEST_HH__
 #define __MEMTEST_HH__
 
-#include "sim/sim_object.hh"
-#include "mem/mem_interface.hh"
-#include "mem/functional_mem/functional_memory.hh"
-#include "cpu/base_cpu.hh"
-#include "cpu/exec_context.hh"
+#include <set>
 
 #include "base/statistics.hh"
+#include "cpu/base_cpu.hh"
+#include "cpu/exec_context.hh"
+#include "mem/functional_mem/functional_memory.hh"
+#include "mem/mem_interface.hh"
+#include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
 class MemTest : public BaseCPU
@@ -87,6 +88,10 @@ class MemTest : public BaseCPU
     unsigned percentCopies;	// target percentage of copy accesses
     unsigned percentUncacheable;
 
+    int id;
+
+    std::set<unsigned> outstandingAddrs;
+
     unsigned blockSize;
 
     Addr blockAddrMask;