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authorSteve Reinhardt <stever@eecs.umich.edu>2006-05-18 22:54:19 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-05-18 22:54:19 -0400
commit86777c9db174c74be49667bce3dda99f8ba23696 (patch)
tree977260677d5e3f726811d919a0b1a36251398a59 /cpu/o3/2bit_local_pred.cc
parent796fa429fef8b038278c4a020374149d8b5ef8eb (diff)
downloadgem5-86777c9db174c74be49667bce3dda99f8ba23696.tar.xz
First steps toward getting full system to work with
TimingSimpleCPU. Not there yet. cpu/simple/atomic.cc: Only read SC result if store was an SC. Don't fake SC here; fake it in PhysicalMemory so all CPU models can share in the joy. cpu/simple/timing.cc: Don't forget to checkForInterrupts(). Only fetch subsequent instruction if we're still running (i.e. not quiesced). dev/io_device.hh: Initialize port pointer in SendEvent object. mem/physical.cc: Move fake SC "implementation" here from AtomicSimpleCPU. mem/request.hh: Initialize flags to all clear, not uninitialized. Otherwise we can't reliably look at flags w/o explicitly setting them every time we create a request. --HG-- extra : convert_revision : ae7601ce6fb54c54e19848aa5391327f9a6e61a6
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