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| author | Korey Sewell <ksewell@umich.edu> | 2006-02-18 23:17:45 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-02-18 23:17:45 -0500 |
| commit | a48c24b61eedf580645ff0294b225d1e69a9444b (patch) | |
| tree | 6c5337e0e6d801a4b5831f56b74293806b61a767 /cpu/o3/alpha_cpu.hh | |
| parent | bd175809286e8da64176da977aeb27fc6ff6d272 (diff) | |
| download | gem5-a48c24b61eedf580645ff0294b225d1e69a9444b.tar.xz | |
Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision : df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Diffstat (limited to 'cpu/o3/alpha_cpu.hh')
0 files changed, 0 insertions, 0 deletions