Updates to bring CPU portion of m5 up-to-date with newmem.

--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4

1 files changed, 18 insertions, 15 deletions

diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 08d42cd46..c563fbef3 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -94,12 +94,10 @@ Param<unsigned> renameWidth;
 Param<unsigned> commitToIEWDelay;
 Param<unsigned> renameToIEWDelay;
 Param<unsigned> issueToExecuteDelay;
+Param<unsigned> dispatchWidth;
 Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
+Param<unsigned> wbWidth;
+Param<unsigned> wbDepth;
 SimObjectParam<FUPool *> fuPool;
 
 Param<unsigned> iewToCommitDelay;
@@ -109,6 +107,9 @@ Param<unsigned> squashWidth;
 Param<Tick> trapLatency;
 Param<Tick> fetchTrapLatency;
 
+Param<unsigned> backComSize;
+Param<unsigned> forwardComSize;
+
 Param<std::string> predType;
 Param<unsigned> localPredictorSize;
 Param<unsigned> localCtrBits;
@@ -219,12 +220,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
                "Issue/Execute/Writeback delay"),
     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
                "to the IEW stage)"),
+    INIT_PARAM(dispatchWidth, "Dispatch width"),
     INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(executeWidth, "Execute width"),
-    INIT_PARAM(executeIntWidth, "Integer execute width"),
-    INIT_PARAM(executeFloatWidth, "Floating point execute width"),
-    INIT_PARAM(executeBranchWidth, "Branch execute width"),
-    INIT_PARAM(executeMemoryWidth, "Memory execute width"),
+    INIT_PARAM(wbWidth, "Writeback width"),
+    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
     INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
 
     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
@@ -235,6 +234,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
     INIT_PARAM_DFLT(fetchTrapLatency, "Number of cycles before the fetch trap is handled", 12),
 
+    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
+    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
+
     INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
     INIT_PARAM(localPredictorSize, "Size of local predictor"),
     INIT_PARAM(localCtrBits, "Bits per counter"),
@@ -353,12 +355,10 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     params->commitToIEWDelay = commitToIEWDelay;
     params->renameToIEWDelay = renameToIEWDelay;
     params->issueToExecuteDelay = issueToExecuteDelay;
+    params->dispatchWidth = dispatchWidth;
     params->issueWidth = issueWidth;
-    params->executeWidth = executeWidth;
-    params->executeIntWidth = executeIntWidth;
-    params->executeFloatWidth = executeFloatWidth;
-    params->executeBranchWidth = executeBranchWidth;
-    params->executeMemoryWidth = executeMemoryWidth;
+    params->wbWidth = wbWidth;
+    params->wbDepth = wbDepth;
     params->fuPool = fuPool;
 
     params->iewToCommitDelay = iewToCommitDelay;
@@ -368,6 +368,9 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     params->trapLatency = trapLatency;
     params->fetchTrapLatency = fetchTrapLatency;
 
+    params->backComSize = backComSize;
+    params->forwardComSize = forwardComSize;
+
     params->predType = predType;
     params->localPredictorSize = localPredictorSize;
     params->localCtrBits = localCtrBits;