shuffle files around for new directory structure

--HG--
rename : cpu/base_cpu.cc => cpu/base.cc
rename : cpu/base_cpu.hh => cpu/base.hh
rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc
rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh
rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc
rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh
rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc
rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh
rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc
rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh
rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh
rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh
rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc
rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh
rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh
rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc
rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh
rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh
rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc
rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh
rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh
rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc
rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh
rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh
rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc
rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh
rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh
rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc
rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh
rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh
rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc
rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh
rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc
rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh
rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh
rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc
rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh
rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh
rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc
rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh
rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh
rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc
rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh
rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh
rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc
rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh
rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh
rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc
rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh
rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc
rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh
rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh
rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc
rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh
rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc
rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh
rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc
rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh
rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc
rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh
rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh
rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc
rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh
rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc
rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh
rename : cpu/full_cpu/smt.hh => cpu/smt.hh
rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh
extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032

1 files changed, 360 insertions, 0 deletions

diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
new file mode 100644
index 000000000..822d58f1f
--- /dev/null
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -0,0 +1,360 @@
+
+#include "base/cprintf.hh"
+#include "base/statistics.hh"
+#include "base/timebuf.hh"
+#include "mem/cache/cache.hh" // for dynamic cast
+#include "mem/mem_interface.hh"
+#include "sim/builder.hh"
+#include "sim/sim_events.hh"
+#include "sim/stats.hh"
+
+#include "cpu/o3/alpha_cpu.hh"
+#include "cpu/o3/alpha_params.hh"
+#include "cpu/o3/comm.hh"
+
+#ifdef FULL_SYSTEM
+#include "arch/alpha/osfpal.hh"
+#include "arch/alpha/isa_traits.hh"
+//#include "arch/alpha/ev5.hh"
+
+//using namespace EV5;
+#endif
+
+template <class Impl>
+AlphaFullCPU<Impl>::AlphaFullCPU(Params &params)
+    : FullBetaCPU<Impl>(params)
+{
+    DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
+
+    this->fetch.setCPU(this);
+    this->decode.setCPU(this);
+    this->rename.setCPU(this);
+    this->iew.setCPU(this);
+    this->commit.setCPU(this);
+
+    this->rob.setCPU(this);
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::regStats()
+{
+    // Register stats for everything that has stats.
+    this->fullCPURegStats();
+    this->fetch.regStats();
+    this->decode.regStats();
+    this->rename.regStats();
+    this->iew.regStats();
+    this->commit.regStats();
+}
+
+#ifndef FULL_SYSTEM
+
+// Will probably need to know which thread is calling syscall
+// Will need to pass that information in to the DynInst when it is constructed,
+// so that this call can be made with the proper thread number.
+template <class Impl>
+void
+AlphaFullCPU<Impl>::syscall(short thread_num)
+{
+    DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
+
+    // Commit stage needs to run as well.
+    this->commit.tick();
+
+    squashStages();
+
+    // Temporarily increase this by one to account for the syscall
+    // instruction.
+    ++(this->funcExeInst);
+
+    // Copy over all important state to xc once all the unrolling is done.
+    copyToXC();
+
+    // This is hardcoded to thread 0 while the CPU is only single threaded.
+    this->thread[0]->syscall();
+
+    // Copy over all important state back to CPU.
+    copyFromXC();
+
+    // Decrease funcExeInst by one as the normal commit will handle
+    // incrememnting it.
+    --(this->funcExeInst);
+}
+
+// This is not a pretty function, and should only be used if it is necessary
+// to fake having everything squash all at once (ie for non-full system
+// syscalls).  Maybe put this at the FullCPU level?
+template <class Impl>
+void
+AlphaFullCPU<Impl>::squashStages()
+{
+    InstSeqNum rob_head = this->rob.readHeadSeqNum();
+
+    // Now hack the time buffer to put this sequence number in the places
+    // where the stages might read it.
+    for (int i = 0; i < 5; ++i)
+    {
+        this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
+    }
+
+    this->fetch.squash(this->rob.readHeadNextPC());
+    this->fetchQueue.advance();
+
+    this->decode.squash();
+    this->decodeQueue.advance();
+
+    this->rename.squash();
+    this->renameQueue.advance();
+    this->renameQueue.advance();
+
+    // Be sure to advance the IEW queues so that the commit stage doesn't
+    // try to set an instruction as completed at the same time that it
+    // might be deleting it.
+    this->iew.squash();
+    this->iewQueue.advance();
+    this->iewQueue.advance();
+    // Needs to tell the LSQ to write back all of its data
+    this->iew.lsqWriteback();
+
+    this->rob.squash(rob_head);
+    this->commit.setSquashing();
+
+    // Now hack the time buffer to clear the sequence numbers in the places
+    // where the stages might read it.?
+    for (int i = 0; i < 5; ++i)
+    {
+        this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
+    }
+
+}
+
+#endif // FULL_SYSTEM
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::copyToXC()
+{
+    PhysRegIndex renamed_reg;
+
+    // First loop through the integer registers.
+    for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
+    {
+        renamed_reg = this->renameMap.lookup(i);
+        this->xc->regs.intRegFile[i] = this->regFile.readIntReg(renamed_reg);
+        DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
+                renamed_reg, this->regFile.intRegFile[renamed_reg]);
+    }
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
+    {
+        renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
+        this->xc->regs.floatRegFile.d[i] =
+            this->regFile.readFloatRegDouble(renamed_reg);
+        this->xc->regs.floatRegFile.q[i] =
+            this->regFile.readFloatRegInt(renamed_reg);
+    }
+
+    this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
+    this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
+    this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
+    this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
+
+    this->xc->regs.pc = this->rob.readHeadPC();
+    this->xc->regs.npc = this->xc->regs.pc+4;
+
+    this->xc->func_exe_inst = this->funcExeInst;
+}
+
+// This function will probably mess things up unless the ROB is empty and
+// there are no instructions in the pipeline.
+template <class Impl>
+void
+AlphaFullCPU<Impl>::copyFromXC()
+{
+    PhysRegIndex renamed_reg;
+
+    // First loop through the integer registers.
+    for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
+    {
+        renamed_reg = this->renameMap.lookup(i);
+
+        DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
+                "now has data %lli.\n",
+                renamed_reg, this->regFile.intRegFile[renamed_reg],
+                this->xc->regs.intRegFile[i]);
+
+        this->regFile.setIntReg(renamed_reg, this->xc->regs.intRegFile[i]);
+    }
+
+    // Then loop through the floating point registers.
+    for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
+    {
+        renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
+        this->regFile.setFloatRegDouble(renamed_reg,
+                                        this->xc->regs.floatRegFile.d[i]);
+        this->regFile.setFloatRegInt(renamed_reg,
+                                     this->xc->regs.floatRegFile.q[i]);
+    }
+
+    // Then loop through the misc registers.
+    this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
+    this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
+    this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
+    this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
+
+    // Then finally set the PC and the next PC.
+//    regFile.pc = xc->regs.pc;
+//    regFile.npc = xc->regs.npc;
+
+    this->funcExeInst = this->xc->func_exe_inst;
+}
+
+#ifdef FULL_SYSTEM
+
+template <class Impl>
+uint64_t *
+AlphaFullCPU<Impl>::getIpr()
+{
+    return this->regFile.getIpr();
+}
+
+template <class Impl>
+uint64_t
+AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
+{
+    return this->regFile.readIpr(idx, fault);
+}
+
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
+{
+    return this->regFile.setIpr(idx, val);
+}
+
+template <class Impl>
+int
+AlphaFullCPU<Impl>::readIntrFlag()
+{
+    return this->regFile.readIntrFlag();
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::setIntrFlag(int val)
+{
+    this->regFile.setIntrFlag(val);
+}
+
+// Can force commit stage to squash and stuff.
+template <class Impl>
+Fault
+AlphaFullCPU<Impl>::hwrei()
+{
+    uint64_t *ipr = getIpr();
+
+    if (!inPalMode())
+        return Unimplemented_Opcode_Fault;
+
+    setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+
+//    kernelStats.hwrei();
+
+    if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+//        AlphaISA::swap_palshadow(&regs, false);
+
+    this->checkInterrupts = true;
+
+    // FIXME: XXX check for interrupts? XXX
+    return No_Fault;
+}
+
+template <class Impl>
+bool
+AlphaFullCPU<Impl>::simPalCheck(int palFunc)
+{
+//    kernelStats.callpal(palFunc);
+
+    switch (palFunc) {
+      case PAL::halt:
+        halt();
+        if (--System::numSystemsRunning == 0)
+            new SimExitEvent("all cpus halted");
+        break;
+
+      case PAL::bpt:
+      case PAL::bugchk:
+        if (this->system->breakpoint())
+            return false;
+        break;
+    }
+
+    return true;
+}
+
+// Probably shouldn't be able to switch to the trap handler as quickly as
+// this.  Also needs to get the exception restart address from the commit
+// stage.
+template <class Impl>
+void
+AlphaFullCPU<Impl>::trap(Fault fault)
+{
+    // Keep in mind that a trap may be initiated by fetch if there's a TLB
+    // miss
+    uint64_t PC = this->commit.readCommitPC();
+
+    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
+    this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+
+//    kernelStats.fault(fault);
+
+    if (fault == Arithmetic_Fault)
+        panic("Arithmetic traps are unimplemented!");
+
+    typename AlphaISA::InternalProcReg *ipr = getIpr();
+
+    // exception restart address - Get the commit PC
+    if (fault != Interrupt_Fault || !inPalMode(PC))
+        ipr[AlphaISA::IPR_EXC_ADDR] = PC;
+
+    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
+        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+        // traps...  skip faulting instruction
+        ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+    }
+
+    if (!inPalMode(PC))
+        swapPALShadow(true);
+
+    this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
+                         AlphaISA::fault_addr[fault] );
+    this->regFile.setNextPC(PC + sizeof(MachInst));
+}
+
+template <class Impl>
+void
+AlphaFullCPU<Impl>::processInterrupts()
+{
+    // Check for interrupts here.  For now can copy the code that exists
+    // within isa_fullsys_traits.hh.
+}
+
+// swap_palshadow swaps in the values of the shadow registers and
+// swaps them with the values of the physical registers that map to the
+// same logical index.
+template <class Impl>
+void
+AlphaFullCPU<Impl>::swapPALShadow(bool use_shadow)
+{
+    if (palShadowEnabled == use_shadow)
+        panic("swap_palshadow: wrong PAL shadow state");
+
+    palShadowEnabled = use_shadow;
+
+    // Will have to lookup in rename map to get physical registers, then
+    // swap.
+}
+
+#endif // FULL_SYSTEM