Merge zizzer:/bk/multiarch

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28

1 files changed, 13 insertions, 13 deletions

diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 3b16975a9..408676331 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
 
 template <class Impl>
 uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
+AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
 {
     return this->regFile.readIpr(idx, fault);
 }
 
 template <class Impl>
-Fault
+Fault *
 AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
 {
     return this->regFile.setIpr(idx, val);
@@ -274,13 +274,13 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
 
 // Can force commit stage to squash and stuff.
 template <class Impl>
-Fault
+Fault *
 AlphaFullCPU<Impl>::hwrei()
 {
     uint64_t *ipr = getIpr();
 
     if (!inPalMode())
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -292,7 +292,7 @@ AlphaFullCPU<Impl>::hwrei()
     this->checkInterrupts = true;
 
     // FIXME: XXX check for interrupts? XXX
-    return No_Fault;
+    return NoFault;
 }
 
 template <class Impl>
@@ -323,28 +323,28 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
 // stage.
 template <class Impl>
 void
-AlphaFullCPU<Impl>::trap(Fault fault)
+AlphaFullCPU<Impl>::trap(Fault * fault)
 {
     // Keep in mind that a trap may be initiated by fetch if there's a TLB
     // miss
     uint64_t PC = this->commit.readCommitPC();
 
-    DPRINTF(Fault, "Fault %s\n", FaultName(fault));
-    this->recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
+    this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
 
 //    kernelStats.fault(fault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
     typename AlphaISA::InternalProcReg *ipr = getIpr();
 
     // exception restart address - Get the commit PC
-    if (fault != Interrupt_Fault || !inPalMode(PC))
+    if (fault != InterruptFault || !inPalMode(PC))
         ipr[AlphaISA::IPR_EXC_ADDR] = PC;
 
-    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == Interrupt_Fault && !PC_PAL(regs.pc) */) {
+    if (fault == PalFault || fault == ArithmeticFault /* ||
+        fault == InterruptFault && !PC_PAL(regs.pc) */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
     }
@@ -353,7 +353,7 @@ AlphaFullCPU<Impl>::trap(Fault fault)
         swapPALShadow(true);
 
     this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
-                         AlphaISA::fault_addr[fault] );
+                         AlphaISA::fault_addr(fault) );
     this->regFile.setNextPC(PC + sizeof(MachInst));
 }