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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
| commit | 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d (patch) | |
| tree | aa785d4b846823e1960c7b308e6de1c90cf6fb3f /cpu/o3/alpha_cpu_impl.hh | |
| parent | 3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff) | |
| download | gem5-8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d.tar.xz | |
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
Diffstat (limited to 'cpu/o3/alpha_cpu_impl.hh')
| -rw-r--r-- | cpu/o3/alpha_cpu_impl.hh | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 6736cf9bc..7ec1ba663 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr() template <class Impl> uint64_t -AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault) +AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault) { return this->regFile.readIpr(idx, fault); } template <class Impl> -Fault * +Fault AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val) { return this->regFile.setIpr(idx, val); @@ -274,7 +274,7 @@ AlphaFullCPU<Impl>::setIntrFlag(int val) // Can force commit stage to squash and stuff. template <class Impl> -Fault * +Fault AlphaFullCPU<Impl>::hwrei() { uint64_t *ipr = getIpr(); @@ -323,7 +323,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc) // stage. template <class Impl> void -AlphaFullCPU<Impl>::trap(Fault * fault) +AlphaFullCPU<Impl>::trap(Fault fault) { // Keep in mind that a trap may be initiated by fetch if there's a TLB // miss |