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authorKevin Lim <ktlim@umich.edu>2006-02-28 15:16:24 -0500
committerKevin Lim <ktlim@umich.edu>2006-02-28 15:16:24 -0500
commit34da58a698e4119876f04d13c337e9974970f49a (patch)
tree6dc9940bf89b04ec973ff4b433a015e13cb7f017 /cpu/o3/alpha_cpu_impl.hh
parent3a362d04b7aed0fa728af9373bad175a096a7de8 (diff)
parent96fd6b5c4039c98a1b536ec184126ad75e7d2539 (diff)
downloadgem5-34da58a698e4119876f04d13c337e9974970f49a.tar.xz
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean arch/alpha/ev5.cc: cpu/o3/regfile.hh: Hand merge. --HG-- rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc extra : convert_revision : c941dd2198851398820b38a66471372ed8454891
Diffstat (limited to 'cpu/o3/alpha_cpu_impl.hh')
-rw-r--r--cpu/o3/alpha_cpu_impl.hh46
1 files changed, 12 insertions, 34 deletions
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 9b7cd8a0e..daa61bb1c 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -179,12 +179,12 @@ AlphaFullCPU<Impl>::copyToXC()
this->xc->regs.floatRegFile.q[i] =
this->regFile.readFloatRegInt(renamed_reg);
}
-
+/*
this->xc->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
this->xc->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
this->xc->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
this->xc->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
-
+*/
this->xc->regs.pc = this->rob.readHeadPC();
this->xc->regs.npc = this->xc->regs.pc+4;
@@ -221,13 +221,13 @@ AlphaFullCPU<Impl>::copyFromXC()
this->regFile.setFloatRegInt(renamed_reg,
this->xc->regs.floatRegFile.q[i]);
}
-
+ /*
// Then loop through the misc registers.
this->regFile.miscRegs.fpcr = this->xc->regs.miscRegs.fpcr;
this->regFile.miscRegs.uniq = this->xc->regs.miscRegs.uniq;
this->regFile.miscRegs.lock_flag = this->xc->regs.miscRegs.lock_flag;
this->regFile.miscRegs.lock_addr = this->xc->regs.miscRegs.lock_addr;
-
+ */
// Then finally set the PC and the next PC.
// regFile.pc = xc->regs.pc;
// regFile.npc = xc->regs.npc;
@@ -238,27 +238,6 @@ AlphaFullCPU<Impl>::copyFromXC()
#if FULL_SYSTEM
template <class Impl>
-uint64_t *
-AlphaFullCPU<Impl>::getIpr()
-{
- return this->regFile.getIpr();
-}
-
-template <class Impl>
-uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
-{
- return this->regFile.readIpr(idx, fault);
-}
-
-template <class Impl>
-Fault
-AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
-{
- return this->regFile.setIpr(idx, val);
-}
-
-template <class Impl>
int
AlphaFullCPU<Impl>::readIntrFlag()
{
@@ -277,16 +256,14 @@ template <class Impl>
Fault
AlphaFullCPU<Impl>::hwrei()
{
- uint64_t *ipr = getIpr();
-
if (!inPalMode())
return new UnimplementedOpcodeFault;
- this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
+ this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
// kernelStats.hwrei();
- if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0)
+ if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
// AlphaISA::swap_palshadow(&regs, false);
this->checkInterrupts = true;
@@ -337,22 +314,23 @@ AlphaFullCPU<Impl>::trap(Fault fault)
if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
- AlphaISA::InternalProcReg *ipr = getIpr();
-
// exception restart address - Get the commit PC
if (!fault->isA<InterruptFault>() || !inPalMode(PC))
- ipr[AlphaISA::IPR_EXC_ADDR] = PC;
+ this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
- ipr[AlphaISA::IPR_EXC_ADDR] += 4;
+ AlphaISA::MiscReg ipr_exc_addr =
+ this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
+ this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
+ ipr_exc_addr + 4);
}
if (!inPalMode(PC))
swapPALShadow(true);
- this->regFile.setPC( ipr[AlphaISA::IPR_PAL_BASE] +
+ this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
(dynamic_cast<AlphaFault *>(fault.get()))->vect());
this->regFile.setNextPC(PC + sizeof(MachInst));
}