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author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-14 16:08:32 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-14 16:08:32 -0500 |
commit | fa763d2ecfae16e84a9f9d689d19f746d84d08e3 (patch) | |
tree | 52474edfd8d1ab010a376b1eb66f4d9990fe4a54 /cpu/o3/alpha_dyn_inst.hh | |
parent | f045b110cf1db6f9fc70589532b48d9cca339897 (diff) | |
parent | efe46430fac2419a02062e3b282324498a55df28 (diff) | |
download | gem5-fa763d2ecfae16e84a9f9d689d19f746d84d08e3.tar.xz |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
cpu/cpu_exec_context.cc:
Hand merge
--HG--
rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh
extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
Diffstat (limited to 'cpu/o3/alpha_dyn_inst.hh')
-rw-r--r-- | cpu/o3/alpha_dyn_inst.hh | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index e7f7d3a57..5b8a05e5c 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -152,19 +152,24 @@ class AlphaDynInst : public BaseDynInst<Impl> return this->cpu->readIntReg(_srcRegIdx[idx]); } - float readFloatRegSingle(const StaticInst *si, int idx) + FloatReg readFloatReg(const StaticInst *si, int idx, int width) { - return this->cpu->readFloatRegSingle(_srcRegIdx[idx]); + return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - double readFloatRegDouble(const StaticInst *si, int idx) + FloatReg readFloatReg(const StaticInst *si, int idx) { - return this->cpu->readFloatRegDouble(_srcRegIdx[idx]); + return this->cpu->readFloatReg(_srcRegIdx[idx]); } - uint64_t readFloatRegInt(const StaticInst *si, int idx) + FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) { - return this->cpu->readFloatRegInt(_srcRegIdx[idx]); + return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); + } + + FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + { + return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } /** @todo: Make results into arrays so they can handle multiple dest @@ -176,21 +181,28 @@ class AlphaDynInst : public BaseDynInst<Impl> this->instResult.integer = val; } - void setFloatRegSingle(const StaticInst *si, int idx, float val) + void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) { - this->cpu->setFloatRegSingle(_destRegIdx[idx], val); + this->cpu->setFloatReg(_destRegIdx[idx], val, width); this->instResult.fp = val; } - void setFloatRegDouble(const StaticInst *si, int idx, double val) + void setFloatReg(const StaticInst *si, int idx, FloatReg val) { - this->cpu->setFloatRegDouble(_destRegIdx[idx], val); + this->cpu->setFloatReg(_destRegIdx[idx], val); this->instResult.dbl = val; } - void setFloatRegInt(const StaticInst *si, int idx, uint64_t val) + void setFloatRegBits(const StaticInst *si, int idx, + FloatRegBits val, int width) + { + this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); + this->instResult.integer = val; + } + + void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) { - this->cpu->setFloatRegInt(_destRegIdx[idx], val); + this->cpu->setFloatRegBits(_destRegIdx[idx], val); this->instResult.integer = val; } |