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authorKorey Sewell <ksewell@umich.edu>2006-02-16 02:40:04 -0500
committerKorey Sewell <ksewell@umich.edu>2006-02-16 02:40:04 -0500
commite7d16b0aefec6543817762b6e5e389372a11b53c (patch)
tree2e90bf447049ece5fb234bfaf44c50515388744e /cpu/o3/alpha_dyn_inst_impl.hh
parent7c9ea671aff141bc0a3e7acc892794e7e8181cf3 (diff)
parent00f451cc02373a22023f1e32ba3823a1d07adb42 (diff)
downloadgem5-e7d16b0aefec6543817762b6e5e389372a11b53c.tar.xz
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch --HG-- extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28
Diffstat (limited to 'cpu/o3/alpha_dyn_inst_impl.hh')
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index d1ebb812d..b20af48cd 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
+AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
-Fault
+Fault *
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
-Fault
+Fault *
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
-AlphaDynInst<Impl>::trap(Fault fault)
+AlphaDynInst<Impl>::trap(Fault * fault)
{
this->cpu->trap(fault);
}