diff options
author | Kevin Lim <ktlim@umich.edu> | 2006-04-22 18:26:48 -0400 |
---|---|---|
committer | Kevin Lim <ktlim@umich.edu> | 2006-04-22 18:26:48 -0400 |
commit | a8b03e4d017b66d7b5502a101ea5b7115827a107 (patch) | |
tree | 9e606dc41a9b84a574d6935e5718c8fe665cc32f /cpu/o3/comm.hh | |
parent | c30f91c2f634a0b55a9b9b9145b1fbe605bb1a02 (diff) | |
download | gem5-a8b03e4d017b66d7b5502a101ea5b7115827a107.tar.xz |
Updates for O3 model.
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
Diffstat (limited to 'cpu/o3/comm.hh')
-rw-r--r-- | cpu/o3/comm.hh | 94 |
1 files changed, 66 insertions, 28 deletions
diff --git a/cpu/o3/comm.hh b/cpu/o3/comm.hh index c74c77ddf..1a8f394ca 100644 --- a/cpu/o3/comm.hh +++ b/cpu/o3/comm.hh @@ -26,30 +26,35 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef __CPU_O3_CPU_COMM_HH__ -#define __CPU_O3_CPU_COMM_HH__ +#ifndef __CPU_O3_COMM_HH__ +#define __CPU_O3_COMM_HH__ #include <vector> +#include "arch/faults.hh" #include "arch/isa_traits.hh" #include "cpu/inst_seq.hh" #include "sim/host.hh" -// Find better place to put this typedef. -// The impl might be the best place for this. +// Typedef for physical register index type. Although the Impl would be the +// most likely location for this, there are a few classes that need this +// typedef yet are not templated on the Impl. For now it will be defined here. typedef short int PhysRegIndex; template<class Impl> -struct SimpleFetchSimpleDecode { +struct DefaultFetchDefaultDecode { typedef typename Impl::DynInstPtr DynInstPtr; int size; DynInstPtr insts[Impl::MaxWidth]; + Fault fetchFault; + InstSeqNum fetchFaultSN; + bool clearFetchFault; }; template<class Impl> -struct SimpleDecodeSimpleRename { +struct DefaultDecodeDefaultRename { typedef typename Impl::DynInstPtr DynInstPtr; int size; @@ -58,7 +63,7 @@ struct SimpleDecodeSimpleRename { }; template<class Impl> -struct SimpleRenameSimpleIEW { +struct DefaultRenameDefaultIEW { typedef typename Impl::DynInstPtr DynInstPtr; int size; @@ -67,19 +72,21 @@ struct SimpleRenameSimpleIEW { }; template<class Impl> -struct SimpleIEWSimpleCommit { +struct DefaultIEWDefaultCommit { typedef typename Impl::DynInstPtr DynInstPtr; int size; DynInstPtr insts[Impl::MaxWidth]; - bool squash; - bool branchMispredict; - bool branchTaken; - uint64_t mispredPC; - uint64_t nextPC; - InstSeqNum squashedSeqNum; + bool squash[Impl::MaxThreads]; + bool branchMispredict[Impl::MaxThreads]; + bool branchTaken[Impl::MaxThreads]; + uint64_t mispredPC[Impl::MaxThreads]; + uint64_t nextPC[Impl::MaxThreads]; + InstSeqNum squashedSeqNum[Impl::MaxThreads]; + + bool includeSquashInst[Impl::MaxThreads]; }; template<class Impl> @@ -91,63 +98,77 @@ struct IssueStruct { DynInstPtr insts[Impl::MaxWidth]; }; +template<class Impl> struct TimeBufStruct { struct decodeComm { bool squash; - bool stall; bool predIncorrect; uint64_t branchAddr; InstSeqNum doneSeqNum; - // Might want to package this kind of branch stuff into a single + // @todo: Might want to package this kind of branch stuff into a single // struct as it is used pretty frequently. bool branchMispredict; bool branchTaken; uint64_t mispredPC; uint64_t nextPC; + + unsigned branchCount; }; - decodeComm decodeInfo; + decodeComm decodeInfo[Impl::MaxThreads]; // Rename can't actually tell anything to squash or send a new PC back // because it doesn't do anything along those lines. But maybe leave // these fields in here to keep the stages mostly orthagonal. struct renameComm { bool squash; - bool stall; uint64_t nextPC; }; - renameComm renameInfo; + renameComm renameInfo[Impl::MaxThreads]; struct iewComm { - bool stall; - // Also eventually include skid buffer space. + bool usedIQ; unsigned freeIQEntries; + bool usedLSQ; + unsigned freeLSQEntries; + + unsigned iqCount; + unsigned ldstqCount; + + unsigned dispatched; + unsigned dispatchedToLSQ; }; - iewComm iewInfo; + iewComm iewInfo[Impl::MaxThreads]; struct commitComm { - bool squash; - bool stall; + bool usedROB; unsigned freeROBEntries; + bool emptyROB; + + bool squash; + bool robSquashing; bool branchMispredict; bool branchTaken; uint64_t mispredPC; uint64_t nextPC; - bool robSquashing; - // Represents the instruction that has either been retired or // squashed. Similar to having a single bus that broadcasts the // retired or squashed sequence number. InstSeqNum doneSeqNum; + //Just in case we want to do a commit/squash on a cycle + //(necessary for multiple ROBs?) + bool commitInsts; + InstSeqNum squashSeqNum; + // Extra bit of information so that the LDSTQ only updates when it // needs to. bool commitIsLoad; @@ -155,9 +176,26 @@ struct TimeBufStruct { // Communication specifically to the IQ to tell the IQ that it can // schedule a non-speculative instruction. InstSeqNum nonSpecSeqNum; + + // Hack for now to send back an uncached access to the IEW stage. + typedef typename Impl::DynInstPtr DynInstPtr; + bool uncached; + DynInstPtr uncachedLoad; + + bool interruptPending; + bool clearInterrupt; }; - commitComm commitInfo; + commitComm commitInfo[Impl::MaxThreads]; + + bool decodeBlock[Impl::MaxThreads]; + bool decodeUnblock[Impl::MaxThreads]; + bool renameBlock[Impl::MaxThreads]; + bool renameUnblock[Impl::MaxThreads]; + bool iewBlock[Impl::MaxThreads]; + bool iewUnblock[Impl::MaxThreads]; + bool commitBlock[Impl::MaxThreads]; + bool commitUnblock[Impl::MaxThreads]; }; -#endif //__CPU_O3_CPU_COMM_HH__ +#endif //__CPU_O3_COMM_HH__ |