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authorKevin Lim <ktlim@umich.edu>2006-05-19 15:53:17 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-19 15:53:17 -0400
commite3d5588ca70c88318c1e41e438102034c92c561e (patch)
tree75886333b22b474893e57254fa00df7a4055df68 /cpu/o3/commit.hh
parent1a6f21b8d23494752cdc9d3a8d1c1a2adfd85ccf (diff)
downloadgem5-e3d5588ca70c88318c1e41e438102034c92c561e.tar.xz
O3 code update/cleanup.
cpu/o3/commit_impl.hh: O3 code update/cleanup. Fetch fault code no longer needed (see previous checkin). --HG-- extra : convert_revision : f602e7f978e19b8900dce482f38f9c7a195e94da
Diffstat (limited to 'cpu/o3/commit.hh')
-rw-r--r--cpu/o3/commit.hh5
1 files changed, 2 insertions, 3 deletions
diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh
index 73eccd2b0..66abf8dc6 100644
--- a/cpu/o3/commit.hh
+++ b/cpu/o3/commit.hh
@@ -30,10 +30,10 @@
#define __CPU_O3_COMMIT_HH__
#include "arch/faults.hh"
-#include "cpu/inst_seq.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/exetrace.hh"
+#include "cpu/inst_seq.hh"
#include "mem/memory_interface.hh"
template <class>
@@ -59,8 +59,7 @@ class O3ThreadState;
* squashing instruction's sequence number, and only broadcasting a
* redirect if it corresponds to an older instruction. Commit also
* supports multiple cycle squashing, to model a ROB that can only
- * remove a certain number of instructions per cycle. Eventually traps
- * and interrupts will most likely be handled here as well.
+ * remove a certain number of instructions per cycle.
*/
template<class Impl>
class DefaultCommit