O3 CPU now handles being used with the sampler.

cpu/o3/2bit_local_pred.cc:
cpu/o3/2bit_local_pred.hh:
cpu/o3/bpred_unit.hh:
cpu/o3/bpred_unit_impl.hh:
cpu/o3/btb.cc:
cpu/o3/btb.hh:
cpu/o3/commit.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/decode.hh:
cpu/o3/decode_impl.hh:
cpu/o3/fetch.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/fu_pool.cc:
cpu/o3/fu_pool.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/inst_queue.hh:
cpu/o3/inst_queue_impl.hh:
cpu/o3/lsq.hh:
cpu/o3/lsq_impl.hh:
cpu/o3/lsq_unit.hh:
cpu/o3/lsq_unit_impl.hh:
cpu/o3/mem_dep_unit.hh:
cpu/o3/mem_dep_unit_impl.hh:
cpu/o3/ras.cc:
cpu/o3/ras.hh:
cpu/o3/rename.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob.hh:
cpu/o3/rob_impl.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/o3/thread_state.hh:
    Handle switching out and taking over.  Needs to be able to reset all state.
cpu/o3/alpha_cpu_impl.hh:
    Handle taking over from another XC.

--HG--
extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449

1 files changed, 36 insertions, 2 deletions

diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index 157e688c7..7834460e2 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -54,6 +54,7 @@ template <class Impl>
 void
 DefaultCommit<Impl>::TrapEvent::process()
 {
+    // This will get reset if it was switched out.
     commit->trapSquash[tid] = true;
 }
 
@@ -75,7 +76,8 @@ DefaultCommit<Impl>::DefaultCommit(Params *params)
       renameWidth(params->renameWidth),
       iewWidth(params->executeWidth),
       commitWidth(params->commitWidth),
-      numThreads(params->numberOfThreads)
+      numThreads(params->numberOfThreads),
+      switchedOut(false)
 {
     _status = Active;
     _nextStatus = Inactive;
@@ -254,6 +256,9 @@ DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
     // Commit must broadcast the number of free entries it has at the start of
     // the simulation, so it starts as active.
     cpu->activateStage(FullCPU::CommitIdx);
+
+    trapLatency = cpu->cycles(6);
+    fetchTrapLatency = cpu->cycles(12);
 }
 
 template <class Impl>
@@ -362,6 +367,29 @@ DefaultCommit<Impl>::initStage()
 
 template <class Impl>
 void
+DefaultCommit<Impl>::switchOut()
+{
+    rob->switchOut();
+}
+
+template <class Impl>
+void
+DefaultCommit<Impl>::takeOverFrom()
+{
+    _status = Active;
+    _nextStatus = Inactive;
+    for (int i=0; i < numThreads; i++) {
+        commitStatus[i] = Idle;
+        changedROBNumEntries[i] = false;
+        trapSquash[i] = false;
+        xcSquash[i] = false;
+    }
+    squashCounter = 0;
+    rob->takeOverFrom();
+}
+
+template <class Impl>
+void
 DefaultCommit<Impl>::updateStatus()
 {
     if (commitStatus[0] == TrapPending ||
@@ -719,8 +747,9 @@ DefaultCommit<Impl>::commit()
     while (threads != (*activeThreads).end()) {
         unsigned tid = *threads++;
 
-        if (fromFetch->fetchFault) {
+        if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
             // Record the fault.  Wait until it's empty in the ROB.  Then handle the trap.
+            // Ignore it if there's already a trap pending as fetch will be redirected.
             fetchFault = fromFetch->fetchFault;
             fetchFaultSN = fromFetch->fetchFaultSN;
             fetchFaultTick = curTick + fetchTrapLatency;
@@ -975,6 +1004,7 @@ DefaultCommit<Impl>::commitInsts()
                 }
 
                 PC[tid] = nextPC[tid];
+                nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
 #if FULL_SYSTEM
                 int count = 0;
                 Addr oldpc;
@@ -1002,6 +1032,10 @@ DefaultCommit<Impl>::commitInsts()
 
     DPRINTF(CommitRate, "%i\n", num_committed);
     numCommittedDist.sample(num_committed);
+
+    if (num_committed == commitWidth) {
+        commit_eligible[0]++;
+    }
 }
 
 template <class Impl>