Code update for CPU models.

arch/alpha/isa_traits.hh:
    Add in clear functions.
cpu/base.cc:
cpu/base.hh:
    Add in CPU progress event.
cpu/base_dyn_inst.hh:
    Mimic normal registers in terms of writing/reading floats.
cpu/checker/cpu.cc:
cpu/checker/cpu.hh:
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Fix up stuff.
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
    Bring up to speed with newmem.
cpu/o3/alpha_cpu_builder.cc:
    Allow for progress intervals.
cpu/o3/tournament_pred.cc:
    Fix up predictor.
cpu/o3/tournament_pred.hh:
cpu/ozone/cpu.hh:
cpu/ozone/cpu_impl.hh:
cpu/simple/cpu.cc:
    Fixes.
cpu/ozone/cpu_builder.cc:
    Allow progress interval.
cpu/ozone/front_end_impl.hh:
    Comment out this message.
cpu/ozone/lw_back_end_impl.hh:
    Remove this.
python/m5/objects/BaseCPU.py:
    Add progress interval.
python/m5/objects/Root.py:
    Allow for stat reset.
sim/serialize.cc:
sim/stat_control.cc:
    Add in stats reset.

--HG--
extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e

1 files changed, 10 insertions, 7 deletions

diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index f1571e61b..0025d4144 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -29,6 +29,7 @@
 #include "config/full_system.hh"
 
 #if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
 #include "sim/system.hh"
 #else
 #include "sim/process.hh"
@@ -598,6 +599,9 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
     // Be sure to signal that there's some activity so the CPU doesn't
     // deschedule itself.
     activityRec.activity();
+    if (thread[tid]->quiesceEvent && thread[tid]->quiesceEvent->scheduled())
+        thread[tid]->quiesceEvent->deschedule();
+
     fetch.wakeFromQuiesce();
 
     _status = Running;
@@ -759,7 +763,6 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
         tickEvent.schedule(curTick);
 }
 
-/*
 template <class Impl>
 void
 FullO3CPU<Impl>::serialize(std::ostream &os)
@@ -771,11 +774,11 @@ FullO3CPU<Impl>::serialize(std::ostream &os)
     // Use SimpleThread's ability to checkpoint to make it easier to
     // write out the registers.  Also make this static so it doesn't
     // get instantiated multiple times (causes a panic in statistics).
-    static SimpleThread temp;
+    static CPUExecContext temp;
 
     for (int i = 0; i < thread.size(); i++) {
         nameOut(os, csprintf("%s.xc.%i", name(), i));
-        temp.copyXC(thread[i]->getXC());
+        temp.copyXC(thread[i]->getXCProxy());
         temp.serialize(os);
     }
 }
@@ -790,15 +793,15 @@ FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
     // Use SimpleThread's ability to checkpoint to make it easier to
     // read in the registers.  Also make this static so it doesn't
     // get instantiated multiple times (causes a panic in statistics).
-    static SimpleThread temp;
+    static CPUExecContext temp;
 
     for (int i = 0; i < thread.size(); i++) {
-        temp.copyXC(thread[i]->getXC());
+        temp.copyXC(thread[i]->getXCProxy());
         temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
-        thread[i]->getXC()->copyArchRegs(temp.getXC());
+        thread[i]->getXCProxy()->copyArchRegs(temp.getProxy());
     }
 }
-*/
+
 template <class Impl>
 uint64_t
 FullO3CPU<Impl>::readIntReg(int reg_idx)