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authorGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
commit0e4a80df1a471671b6ef7003e29124b6835ade42 (patch)
tree1d2c44d8c3462dd94c0fbf6e4f149e026c901aa8 /cpu/o3/cpu.hh
parenta48c24b61eedf580645ff0294b225d1e69a9444b (diff)
parent463aa6d49d49ba9c383f07207df57bad75c58ec9 (diff)
downloadgem5-0e4a80df1a471671b6ef7003e29124b6835ade42.tar.xz
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
Diffstat (limited to 'cpu/o3/cpu.hh')
-rw-r--r--cpu/o3/cpu.hh5
1 files changed, 2 insertions, 3 deletions
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 75dca5056..321d61dce 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -78,7 +78,6 @@ class FullO3CPU : public BaseFullCPU
{
public:
//Put typedefs from the Impl here.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPolicy;
typedef typename Impl::Params Params;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -153,11 +152,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
- { return ITB_ASN_ASN(regFile.getIpr()[ISA::IPR_ITB_ASN]); }
+ { return ITB_ASN_ASN(regFile.getIpr()[TheISA::IPR_ITB_ASN]); }
/** Get data asid. */
int getDataAsid()
- { return DTB_ASN_ASN(regFile.getIpr()[ISA::IPR_DTB_ASN]); }
+ { return DTB_ASN_ASN(regFile.getIpr()[TheISA::IPR_DTB_ASN]); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }