Pushed ev5.hh out of the non-alpha code.

arch/SConscript:
    ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
    Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
    Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
    Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
    Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.

--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd

1 files changed, 2 insertions, 7 deletions

diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 02908887e..31a1b604b 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -49,11 +49,6 @@
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#if FULL_SYSTEM
-#include "arch/ev5.hh"
-using namespace EV5;
-#endif
-
 class FunctionalMemory;
 class Process;
 
@@ -152,11 +147,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
+    { return regFile.miscRegs.getInstAsid(); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
+    { return regFile.miscRegs.getDataAsid(); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }