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authorKevin Lim <ktlim@umich.edu>2006-05-31 11:45:02 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-31 11:45:02 -0400
commita514bf21508f4398f5cf7322f5f2a1ed212bbcaa (patch)
treee41f2e45926a5724765f762fe8c4b34e9e4d5c56 /cpu/o3/cpu_policy.hh
parent94eff2f4854ce23900bcc3d694ff4c290111bea7 (diff)
downloadgem5-a514bf21508f4398f5cf7322f5f2a1ed212bbcaa.tar.xz
Comments and code cleanup.
cpu/activity.cc: cpu/activity.hh: cpu/o3/alpha_cpu.hh: Updates to include comments. cpu/base_dyn_inst.cc: Remove call to thread->misspeculating(), as it's never actually misspeculating. --HG-- extra : convert_revision : 86574d684770fac9b480475acca048ea418cdac3
Diffstat (limited to 'cpu/o3/cpu_policy.hh')
-rw-r--r--cpu/o3/cpu_policy.hh28
1 files changed, 27 insertions, 1 deletions
diff --git a/cpu/o3/cpu_policy.hh b/cpu/o3/cpu_policy.hh
index b4249b12d..c30e58389 100644
--- a/cpu/o3/cpu_policy.hh
+++ b/cpu/o3/cpu_policy.hh
@@ -48,24 +48,50 @@
#include "cpu/o3/comm.hh"
+/**
+ * Struct that defines the key classes to be used by the CPU. All
+ * classes use the typedefs defined here to determine what are the
+ * classes of the other stages and communication buffers. In order to
+ * change a structure such as the IQ, simply change the typedef here
+ * to use the desired class instead, and recompile. In order to
+ * create a different CPU to be used simultaneously with this one, see
+ * the alpha_impl.hh file for instructions.
+ */
template<class Impl>
struct SimpleCPUPolicy
{
+ /** Typedef for the branch prediction unit (which includes the BP,
+ * RAS, and BTB).
+ */
typedef BPredUnit<Impl> BPredUnit;
+ /** Typedef for the register file. Most classes assume a unified
+ * physical register file.
+ */
typedef PhysRegFile<Impl> RegFile;
+ /** Typedef for the freelist of registers. */
typedef SimpleFreeList FreeList;
+ /** Typedef for the rename map. */
typedef SimpleRenameMap RenameMap;
+ /** Typedef for the ROB. */
typedef ROB<Impl> ROB;
+ /** Typedef for the instruction queue/scheduler. */
typedef InstructionQueue<Impl> IQ;
+ /** Typedef for the memory dependence unit. */
typedef MemDepUnit<StoreSet, Impl> MemDepUnit;
+ /** Typedef for the LSQ. */
typedef LSQ<Impl> LSQ;
+ /** Typedef for the thread-specific LSQ units. */
typedef LSQUnit<Impl> LSQUnit;
-
+ /** Typedef for fetch. */
typedef DefaultFetch<Impl> Fetch;
+ /** Typedef for decode. */
typedef DefaultDecode<Impl> Decode;
+ /** Typedef for rename. */
typedef DefaultRename<Impl> Rename;
+ /** Typedef for Issue/Execute/Writeback. */
typedef DefaultIEW<Impl> IEW;
+ /** Typedef for commit. */
typedef DefaultCommit<Impl> Commit;
/** The struct for communication between fetch and decode. */