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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 20:10:40 -0500 |
| commit | 8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d (patch) | |
| tree | aa785d4b846823e1960c7b308e6de1c90cf6fb3f /cpu/o3/fetch_impl.hh | |
| parent | 3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff) | |
| download | gem5-8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d.tar.xz | |
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
Diffstat (limited to 'cpu/o3/fetch_impl.hh')
| -rw-r--r-- | cpu/o3/fetch_impl.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index e8d333ed4..8029fc732 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC) } template <class Impl> -Fault * +Fault SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) { // Check if the instruction exists within the cache. @@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC) unsigned flags = 0; #endif // FULL_SYSTEM - Fault * fault = NoFault; + Fault fault = NoFault; // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); @@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch() Addr fetch_PC = cpu->readPC(); // Fault code for memory access. - Fault * fault = NoFault; + Fault fault = NoFault; // If returning from the delay of a cache miss, then update the status // to running, otherwise do the cache access. Possibly move this up |