Updates to bring CPU portion of m5 up-to-date with newmem.

--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4

1 files changed, 72 insertions, 35 deletions

diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index eda6a6bc0..d21c573fe 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -224,6 +224,47 @@ class DefaultIEW
     /** Returns if the LSQ has any stores to writeback. */
     bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
 
+    void incrWb(InstSeqNum &sn)
+    {
+        if (++wbOutstanding == wbMax)
+            ableToIssue = false;
+        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
+        assert(wbOutstanding <= wbMax);
+#ifdef DEBUG
+        wbList.insert(sn);
+#endif
+    }
+
+    void decrWb(InstSeqNum &sn)
+    {
+        if (wbOutstanding-- == wbMax)
+            ableToIssue = true;
+        DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
+        assert(wbOutstanding >= 0);
+#ifdef DEBUG
+        assert(wbList.find(sn) != wbList.end());
+        wbList.erase(sn);
+#endif
+    }
+
+#ifdef DEBUG
+    std::set<InstSeqNum> wbList;
+
+    void dumpWb()
+    {
+        std::set<InstSeqNum>::iterator wb_it = wbList.begin();
+        while (wb_it != wbList.end()) {
+            cprintf("[sn:%lli]\n",
+                    (*wb_it));
+            wb_it++;
+        }
+    }
+#endif
+
+    bool canIssue() { return ableToIssue; }
+
+    bool ableToIssue;
+
   private:
     /** Sends commit proper information for a squash due to a branch
      * mispredict.
@@ -281,6 +322,9 @@ class DefaultIEW
     /** Processes inputs and changes state accordingly. */
     void checkSignalsAndUpdate(unsigned tid);
 
+    /** Removes instructions from rename from a thread's instruction list. */
+    void emptyRenameInsts(unsigned tid);
+
     /** Sorts instructions coming from rename into lists separated by thread. */
     void sortInsts();
 
@@ -401,20 +445,12 @@ class DefaultIEW
      */
     unsigned issueToExecuteDelay;
 
-    /** Width of issue's read path, in instructions.  The read path is both
-     *  the skid buffer and the rename instruction queue.
-     *  Note to self: is this really different than issueWidth?
-     */
-    unsigned issueReadWidth;
+    /** Width of dispatch, in instructions. */
+    unsigned dispatchWidth;
 
     /** Width of issue, in instructions. */
     unsigned issueWidth;
 
-    /** Width of execute, in instructions.  Might make more sense to break
-     *  down into FP vs int.
-     */
-    unsigned executeWidth;
-
     /** Index into queue of instructions being written back. */
     unsigned wbNumInst;
 
@@ -425,6 +461,17 @@ class DefaultIEW
      */
     unsigned wbCycle;
 
+    /** Number of instructions in flight that will writeback. */
+    int wbOutstanding;
+
+    /** Writeback width. */
+    unsigned wbWidth;
+
+    /** Writeback width * writeback depth, where writeback depth is
+     * the number of cycles of writing back instructions that can be
+     * buffered. */
+    unsigned wbMax;
+
     /** Number of active threads. */
     unsigned numThreads;
 
@@ -459,14 +506,6 @@ class DefaultIEW
     Stats::Scalar<> iewIQFullEvents;
     /** Stat for number of times the LSQ becomes full. */
     Stats::Scalar<> iewLSQFullEvents;
-    /** Stat for total number of executed instructions. */
-    Stats::Scalar<> iewExecutedInsts;
-    /** Stat for total number of executed load instructions. */
-    Stats::Vector<> iewExecLoadInsts;
-    /** Stat for total number of executed store instructions. */
-//    Stats::Scalar<> iewExecStoreInsts;
-    /** Stat for total number of squashed instructions skipped at execute. */
-    Stats::Scalar<> iewExecSquashedInsts;
     /** Stat for total number of memory ordering violation events. */
     Stats::Scalar<> memOrderViolationEvents;
     /** Stat for total number of incorrect predicted taken branches. */
@@ -476,28 +515,27 @@ class DefaultIEW
     /** Stat for total number of mispredicted branches detected at execute. */
     Stats::Formula branchMispredicts;
 
+    /** Stat for total number of executed instructions. */
+    Stats::Scalar<> iewExecutedInsts;
+    /** Stat for total number of executed load instructions. */
+    Stats::Vector<> iewExecLoadInsts;
+    /** Stat for total number of executed store instructions. */
+//    Stats::Scalar<> iewExecStoreInsts;
+    /** Stat for total number of squashed instructions skipped at execute. */
+    Stats::Scalar<> iewExecSquashedInsts;
     /** Number of executed software prefetches. */
-    Stats::Vector<> exeSwp;
+    Stats::Vector<> iewExecutedSwp;
     /** Number of executed nops. */
-    Stats::Vector<> exeNop;
+    Stats::Vector<> iewExecutedNop;
     /** Number of executed meomory references. */
-    Stats::Vector<> exeRefs;
+    Stats::Vector<> iewExecutedRefs;
     /** Number of executed branches. */
-    Stats::Vector<> exeBranches;
-
-//    Stats::Vector<> issued_ops;
-/*
-    Stats::Vector<> stat_fu_busy;
-    Stats::Vector2d<> stat_fuBusy;
-    Stats::Vector<> dist_unissued;
-    Stats::Vector2d<> stat_issued_inst_type;
-*/
-    /** Number of instructions issued per cycle. */
-    Stats::Formula issueRate;
+    Stats::Vector<> iewExecutedBranches;
     /** Number of executed store instructions. */
     Stats::Formula iewExecStoreInsts;
-//    Stats::Formula issue_op_rate;
-//    Stats::Formula fu_busy_rate;
+    /** Number of instructions executed per cycle. */
+    Stats::Formula iewExecRate;
+
     /** Number of instructions sent to commit. */
     Stats::Vector<> iewInstsToCommit;
     /** Number of instructions that writeback. */
@@ -510,7 +548,6 @@ class DefaultIEW
      * to resource contention.
      */
     Stats::Vector<> wbPenalized;
-
     /** Number of instructions per cycle written back. */
     Stats::Formula wbRate;
     /** Average number of woken instructions per writeback. */