Minor changes plus updates to O3.

cpu/base.cc:
    Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Be sure to include all parameters.
cpu/o3/cpu.cc:
    IEW also needs to switch out.
cpu/o3/iew_impl.hh:
    Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
    Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
    Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
    Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
    Switch out fix.

--HG--
extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a

1 files changed, 15 insertions, 3 deletions

diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index 102be4f8d..33fd0f6b9 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -431,6 +431,8 @@ DefaultIEW<Impl>::doSwitchOut()
 {
     // Clear any state.
     switchedOut = true;
+    assert(insts[0].empty());
+    assert(skidBuffer[0].empty());
 
     instQueue.switchOut();
     ldstQueue.switchOut();
@@ -1281,13 +1283,23 @@ DefaultIEW<Impl>::executeInsts()
                 // event adds the instruction to the queue to commit
                 fault = ldstQueue.executeLoad(inst);
             } else if (inst->isStore()) {
-                ldstQueue.executeStore(inst);
+                fault = ldstQueue.executeStore(inst);
 
                 // If the store had a fault then it may not have a mem req
-                if (inst->req && !(inst->req->flags & LOCKED)) {
+                if (!inst->isStoreConditional() && fault == NoFault) {
                     inst->setExecuted();
 
                     instToCommit(inst);
+                } else if (fault != NoFault) {
+                    // If the instruction faulted, then we need to send it along to commit
+                    // without the instruction completing.
+
+                    // Send this instruction to commit, also make sure iew stage
+                    // realizes there is activity.
+                    inst->setExecuted();
+
+                    instToCommit(inst);
+                    activityThisCycle();
                 }
 
                 // Store conditionals will mark themselves as
@@ -1408,7 +1420,7 @@ DefaultIEW<Impl>::writebackInsts()
         // E.g. Uncached loads have not actually executed when they
         // are first sent to commit.  Instead commit must tell the LSQ
         // when it's ready to execute the uncached load.
-        if (!inst->isSquashed() && inst->isExecuted()) {
+        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
             int dependents = instQueue.wakeDependents(inst);
 
             for (int i = 0; i < inst->numDestRegs(); i++) {