Minor changes plus updates to O3.

cpu/base.cc:
    Have output message regardless of build.
cpu/checker/cpu_builder.cc:
cpu/checker/o3_cpu_builder.cc:
    Be sure to include all parameters.
cpu/o3/cpu.cc:
    IEW also needs to switch out.
cpu/o3/iew_impl.hh:
    Handle stores with faults properly.
cpu/o3/inst_queue_impl.hh:
    Switch out properly, handle squashing properly.
cpu/o3/lsq_unit_impl.hh:
    Minor fixes.
cpu/o3/mem_dep_unit_impl.hh:
    Make sure mem dep unit is switched out properly.
cpu/o3/rename_impl.hh:
    Switch out fix.

--HG--
extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a

1 files changed, 16 insertions, 5 deletions

diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh
index b6b06ca77..0a17cae5c 100644
--- a/cpu/o3/inst_queue_impl.hh
+++ b/cpu/o3/inst_queue_impl.hh
@@ -386,8 +386,16 @@ template <class Impl>
 void
 InstructionQueue<Impl>::switchOut()
 {
+/*
+    if (!instList[0].empty() || (numEntries != freeEntries) ||
+        !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
+        dumpInsts();
+//        assert(0);
+    }
+*/
     resetState();
     dependGraph.reset();
+    instsToExecute.clear();
     switchedOut = true;
     for (int i = 0; i < numThreads; ++i) {
         memDepUnit[i].switchOut();
@@ -643,9 +651,12 @@ template <class Impl>
 void
 InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
 {
+    DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
     // The CPU could have been sleeping until this op completed (*extremely*
     // long latency op).  Wake it if it was.  This may be overkill.
     if (isSwitchedOut()) {
+        DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
+                inst->seqNum);
         return;
     }
 
@@ -1033,6 +1044,10 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
             (squashed_inst->isMemRef() &&
              !squashed_inst->memOpDone)) {
 
+            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
+                    "squashed.\n",
+                    tid, squashed_inst->seqNum, squashed_inst->readPC());
+
             // Remove the instruction from the dependency list.
             if (!squashed_inst->isNonSpeculative() &&
                 !squashed_inst->isStoreConditional() &&
@@ -1063,7 +1078,7 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
 
                     ++iqSquashedOperandsExamined;
                 }
-            } else {
+            } else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) {
                 NonSpecMapIt ns_inst_it =
                     nonSpecInsts.find(squashed_inst->seqNum);
                 assert(ns_inst_it != nonSpecInsts.end());
@@ -1090,10 +1105,6 @@ InstructionQueue<Impl>::doSquash(unsigned tid)
             count[squashed_inst->threadNumber]--;
 
             ++freeEntries;
-
-            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
-                    "squashed.\n",
-                    tid, squashed_inst->seqNum, squashed_inst->readPC());
         }
 
         instList[tid].erase(squash_it--);