Small fixes to O3 model.

cpu/o3/alpha_dyn_inst.hh:
    Set the instResult using a function on the base dyn inst.
cpu/o3/bpred_unit_impl.hh:
    Don't need to reset the state.
cpu/o3/commit_impl.hh:
    Mark instructions as completed.

    Wait until all stores are written back to handle a fault.
cpu/o3/cpu.cc:
    Clear instruction lists when switching out.
cpu/o3/lsq_unit.hh:
    Allow wbEvent to be set externally.
cpu/o3/lsq_unit_impl.hh:
    Mark instructions as completed properly.  Also use events for writing back stores even if there is a hit in the dcache.

--HG--
extra : convert_revision : 172ad088b75ac31e848a5040633152b5c051444c

1 files changed, 15 insertions, 24 deletions

diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh
index c5ce34c70..3bb9a81f8 100644
--- a/cpu/o3/lsq_unit_impl.hh
+++ b/cpu/o3/lsq_unit_impl.hh
@@ -672,11 +672,6 @@ LSQUnit<Impl>::writebackStores()
                 req->paddr, *(req->data),
                 storeQueue[storeWBIdx].inst->seqNum);
 
-//        if (fault != NoFault) {
-            //What should we do if there is a fault???
-            //for now panic
-//            panic("Page Table Fault!!!!!\n");
-//        }
         switch(storeQueue[storeWBIdx].size) {
           case 1:
             cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
@@ -693,8 +688,16 @@ LSQUnit<Impl>::writebackStores()
           default:
             panic("Unexpected store size!\n");
         }
+        if (!(req->flags & LOCKED)) {
+            storeQueue[storeWBIdx].inst->setCompleted();
+        }
 
         if (dcacheInterface) {
+            assert(!req->completionEvent);
+            StoreCompletionEvent *store_event = new
+                StoreCompletionEvent(storeWBIdx, NULL, this);
+            req->completionEvent = store_event;
+
             MemAccessResult result = dcacheInterface->access(req);
 
             if (isStalled() &&
@@ -710,16 +713,12 @@ LSQUnit<Impl>::writebackStores()
             if (result != MA_HIT && dcacheInterface->doEvents()) {
                 typename IEW::LdWritebackEvent *wb = NULL;
                 if (req->flags & LOCKED) {
-                    // Stx_C does not generate a system port transaction.
-/*
-                    if (cpu->lockFlag && cpu->lockAddr == req->paddr) {
-                        req->result=1;
-                    } else {
-                        req->result = 0;
-                    }
-*/
-                    wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
-                                                            iewStage);
+                    // Stx_C should not generate a system port transaction,
+                    // but that might be hard to accomplish.
+                    wb = new typename
+                        IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
+                                              iewStage);
+                    store_event->wbEvent = wb;
                 }
 
                 DPRINTF(LSQUnit,"D-Cache Write Miss!\n");
@@ -727,12 +726,6 @@ LSQUnit<Impl>::writebackStores()
                 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
                         storeQueue[storeWBIdx].inst->seqNum);
 
-                // Will stores need their own kind of writeback events?
-                // Do stores even need writeback events?
-                assert(!req->completionEvent);
-                req->completionEvent = new
-                    StoreCompletionEvent(storeWBIdx, wb, this);
-
                 lastDcacheStall = curTick;
 
 //                _status = DcacheMissStall;
@@ -766,10 +759,8 @@ LSQUnit<Impl>::writebackStores()
                     typename IEW::LdWritebackEvent *wb =
                         new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
                                                            iewStage);
-                    wb->schedule(curTick);
+                    store_event->wbEvent = wb;
                 }
-
-                completeStore(storeWBIdx);
             }
 
             incrStIdx(storeWBIdx);