summaryrefslogtreecommitdiff
path: root/cpu/o3/lsq_unit_impl.hh
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-05-16 14:06:35 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-16 14:06:35 -0400
commitef6e2eb3c4dbf337df7380ae93360c13140f11f6 (patch)
tree9f7d6b6f3bb38733c2b15d500cc90229263f3afd /cpu/o3/lsq_unit_impl.hh
parentc23b23f4e7f9f0faec555cb282c899b77223a110 (diff)
downloadgem5-ef6e2eb3c4dbf337df7380ae93360c13140f11f6.tar.xz
Updates for sampler, checker, and general correctness.
cpu/o3/alpha_cpu.hh: Update for sampler to work properly. Also code cleanup. cpu/o3/alpha_cpu_builder.cc: cpu/o3/alpha_dyn_inst.hh: Updates to support the checker. cpu/o3/alpha_cpu_impl.hh: Updates to support the checker. Also general code cleanup. cpu/o3/alpha_dyn_inst_impl.hh: Code cleanup. cpu/o3/alpha_params.hh: Updates to support the checker. Also supports trap latencies set through the parameters. cpu/o3/commit.hh: Supports sampler, checker. Code cleanup. cpu/o3/commit_impl.hh: Updates to support the sampler and checker, as well as general code cleanup. cpu/o3/cpu.cc: cpu/o3/cpu.hh: Support sampler and checker. cpu/o3/decode_impl.hh: Supports sampler. cpu/o3/fetch.hh: Supports sampler. Also update to hold the youngest valid SN fetch has seen to ensure that the entire pipeline has been drained. cpu/o3/fetch_impl.hh: Sampler updates. Also be sure to not fetches to uncached space (bad path). cpu/o3/iew.hh: cpu/o3/iew_impl.hh: Sampler updates. cpu/o3/lsq_unit_impl.hh: Supports checker. cpu/o3/regfile.hh: No need for accessing xcProxies directly. cpu/o3/rename.hh: cpu/o3/rename_impl.hh: Sampler support. --HG-- extra : convert_revision : 03881885dd50ebbca13ef31f31492fd4ef59121c
Diffstat (limited to 'cpu/o3/lsq_unit_impl.hh')
-rw-r--r--cpu/o3/lsq_unit_impl.hh9
1 files changed, 9 insertions, 0 deletions
diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh
index 3bb9a81f8..dca808ac9 100644
--- a/cpu/o3/lsq_unit_impl.hh
+++ b/cpu/o3/lsq_unit_impl.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "cpu/checker/cpu.hh"
#include "cpu/o3/lsq_unit.hh"
#include "base/str.hh"
@@ -690,6 +691,9 @@ LSQUnit<Impl>::writebackStores()
}
if (!(req->flags & LOCKED)) {
storeQueue[storeWBIdx].inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick(storeQueue[storeWBIdx].inst);
+ }
}
if (dcacheInterface) {
@@ -937,6 +941,11 @@ LSQUnit<Impl>::completeStore(int store_idx)
stallingStoreIsn = 0;
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
}
+
+ storeQueue[store_idx].inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick(storeQueue[store_idx].inst);
+ }
}
template <class Impl>