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author | Kevin Lim <ktlim@umich.edu> | 2006-04-22 18:26:48 -0400 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-04-22 18:26:48 -0400 |
commit | a8b03e4d017b66d7b5502a101ea5b7115827a107 (patch) | |
tree | 9e606dc41a9b84a574d6935e5718c8fe665cc32f /cpu/o3/mem_dep_unit.cc | |
parent | c30f91c2f634a0b55a9b9b9145b1fbe605bb1a02 (diff) | |
download | gem5-a8b03e4d017b66d7b5502a101ea5b7115827a107.tar.xz |
Updates for O3 model.
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
Diffstat (limited to 'cpu/o3/mem_dep_unit.cc')
-rw-r--r-- | cpu/o3/mem_dep_unit.cc | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/cpu/o3/mem_dep_unit.cc b/cpu/o3/mem_dep_unit.cc index 9c1e7f9d8..ccdd1a515 100644 --- a/cpu/o3/mem_dep_unit.cc +++ b/cpu/o3/mem_dep_unit.cc @@ -34,3 +34,13 @@ // Force instantation of memory dependency unit using store sets and // AlphaSimpleImpl. template class MemDepUnit<StoreSet, AlphaSimpleImpl>; + +template <> +int +MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_count = 0; +template <> +int +MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_insert = 0; +template <> +int +MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_erase = 0; |