Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.

arch/alpha/arguments.cc:
    Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
    Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
    Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
    Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
    Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
    Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
    Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
    Replaced setFloatRegDouble with setFloatReg

--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2

1 files changed, 57 insertions, 23 deletions

diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 1e6e10f29..a5cfa8f3c 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -89,43 +89,64 @@ class PhysRegFile
         return intRegFile[reg_idx];
     }
 
-    float readFloatRegSingle(PhysRegIndex reg_idx)
+    FloatReg readFloatReg(PhysRegIndex reg_idx, int width)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Access to float register %i as single, has "
-                "data %8.8f\n", int(reg_idx), (float)floatRegFile[reg_idx].d);
+        FloatReg floatReg = floatRegFile.readReg(reg_idx, width);
 
-        return (float)floatRegFile[reg_idx].d;
+        DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has "
+                "data %8.8d\n", int(reg_idx), (double)floatReg);
+
+        return floatReg;
     }
 
-    double readFloatRegDouble(PhysRegIndex reg_idx)
+    FloatReg readFloatReg(PhysRegIndex reg_idx)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Access to float register %i as double, has "
-                " data %8.8f\n", int(reg_idx), floatRegFile[reg_idx].d);
+        FloatReg floatReg = floatRegFile.readReg(reg_idx);
+
+        DPRINTF(IEW, "RegFile: Access to float register %i, has "
+                "data %8.8d\n", int(reg_idx), (double)floatReg);
 
-        return floatRegFile[reg_idx].d;
+        return floatReg;
     }
 
-    uint64_t readFloatRegInt(PhysRegIndex reg_idx)
+    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Access to float register %i as int, has data "
-                "%lli\n", int(reg_idx), floatRegFile[reg_idx].q);
+        FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx, width);
+
+        DPRINTF(IEW, "RegFile: Access to %d byte float register %i as int, "
+                "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
+
+        return floatRegBits;
+    }
+
+    FloatRegBits readFloatRegBits(PhysRegIndex reg_idx)
+    {
+        // Remove the base Float reg dependency.
+        reg_idx = reg_idx - numPhysicalIntRegs;
+
+        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+
+        FloatRegBits floatRegBits = floatRegFile.readRegBits(reg_idx);
+
+        DPRINTF(IEW, "RegFile: Access to float register %i as int, "
+                "has data %lli\n", int(reg_idx), (uint64_t)floatRegBits);
 
-        return floatRegFile[reg_idx].q;
+        return floatRegBits;
     }
 
     void setIntReg(PhysRegIndex reg_idx, uint64_t val)
@@ -138,33 +159,33 @@ class PhysRegFile
         intRegFile[reg_idx] = val;
     }
 
-    void setFloatRegSingle(PhysRegIndex reg_idx, float val)
+    void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
-                int(reg_idx), val);
+        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
+                int(reg_idx), (double)val);
 
-        floatRegFile[reg_idx].d = (double)val;
+        floatRegFile.setReg(reg_idx, val, width);
     }
 
-    void setFloatRegDouble(PhysRegIndex reg_idx, double val)
+    void setFloatReg(PhysRegIndex reg_idx, FloatReg val)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
 
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
-        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8f\n",
-                int(reg_idx), val);
+        DPRINTF(IEW, "RegFile: Setting float register %i to %8.8d\n",
+                int(reg_idx), (double)val);
 
-        floatRegFile[reg_idx].d = val;
+        floatRegFile.setReg(reg_idx, val);
     }
 
-    void setFloatRegInt(PhysRegIndex reg_idx, uint64_t val)
+    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width)
     {
         // Remove the base Float reg dependency.
         reg_idx = reg_idx - numPhysicalIntRegs;
@@ -172,9 +193,22 @@ class PhysRegFile
         assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
 
         DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
-                int(reg_idx), val);
+                int(reg_idx), (uint64_t)val);
+
+        floatRegFile.setRegBits(reg_idx, val, width);
+    }
+
+    void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val)
+    {
+        // Remove the base Float reg dependency.
+        reg_idx = reg_idx - numPhysicalIntRegs;
+
+        assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+
+        DPRINTF(IEW, "RegFile: Setting float register %i to %lli\n",
+                int(reg_idx), (uint64_t)val);
 
-        floatRegFile[reg_idx].q = val;
+        floatRegFile.setRegBits(reg_idx, val);
     }
 
     uint64_t readPC()