Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.

arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45

1 files changed, 147 insertions, 143 deletions

diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 5aafd5495..655a3cad9 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -52,6 +52,11 @@ using namespace EV5;
 template <class Impl>
 class PhysRegFile
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::IntReg IntReg;
+    typedef TheISA::FloatReg FloatReg;
+    typedef TheISA::MiscRegFile MiscRegFile;
     //Note that most of the definitions of the IntReg, FloatReg, etc. exist
     //within the Impl/ISA class and not within this PhysRegFile class.
 
@@ -62,7 +67,6 @@ class PhysRegFile
     //Will make these registers public for now, but they probably should
     //be private eventually with some accessor functions.
   public:
-    typedef typename Impl::ISA ISA;
     typedef typename Impl::FullCPU FullCPU;
 
     PhysRegFile(unsigned _numPhysicalIntRegs,
@@ -281,73 +285,73 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
     uint64_t retval = 0;    // return value, default 0
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PALtemp23:
-      case ISA::IPR_PAL_BASE:
-
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
-      case ISA::IPR_ISR:
-      case ISA::IPR_EXC_ADDR:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_MCSR:
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
-      case ISA::IPR_SIRR:
-      case ISA::IPR_ICSR:
-      case ISA::IPR_ICM:
-      case ISA::IPR_DTB_CM:
-      case ISA::IPR_IPLR:
-      case ISA::IPR_INTID:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PALtemp23:
+      case TheISA::IPR_PAL_BASE:
+
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
+      case TheISA::IPR_ISR:
+      case TheISA::IPR_EXC_ADDR:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_MCSR:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
+      case TheISA::IPR_SIRR:
+      case TheISA::IPR_ICSR:
+      case TheISA::IPR_ICM:
+      case TheISA::IPR_DTB_CM:
+      case TheISA::IPR_IPLR:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_PMCTR:
         // no side-effect
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
         retval |= curTick  & ULL(0x00000000ffffffff);
         break;
 
-      case ISA::IPR_VA:
+      case TheISA::IPR_VA:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_VA_FORM:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_IFAULT_VA_FORM:
-      case ISA::IPR_EXC_MASK:
-      case ISA::IPR_EXC_SUM:
+      case TheISA::IPR_VA_FORM:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_IFAULT_VA_FORM:
+      case TheISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
         retval = ipr[idx];
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         {
-            typename ISA::PTE &pte = cpu->dtb->index(1);
+            TheISA::PTE &pte = cpu->dtb->index(1);
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -360,15 +364,15 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
         break;
 
         // write only registers
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
-      case ISA::IPR_ALT_MODE:
-      case ISA::IPR_DTB_IA:
-      case ISA::IPR_DTB_IAP:
-      case ISA::IPR_ITB_IA:
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
+      case TheISA::IPR_ALT_MODE:
+      case TheISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IAP:
+      case TheISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IAP:
         fault = UnimplementedOpcodeFault;
         break;
 
@@ -390,195 +394,195 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     uint64_t old;
 
     switch (idx) {
-      case ISA::IPR_PALtemp0:
-      case ISA::IPR_PALtemp1:
-      case ISA::IPR_PALtemp2:
-      case ISA::IPR_PALtemp3:
-      case ISA::IPR_PALtemp4:
-      case ISA::IPR_PALtemp5:
-      case ISA::IPR_PALtemp6:
-      case ISA::IPR_PALtemp7:
-      case ISA::IPR_PALtemp8:
-      case ISA::IPR_PALtemp9:
-      case ISA::IPR_PALtemp10:
-      case ISA::IPR_PALtemp11:
-      case ISA::IPR_PALtemp12:
-      case ISA::IPR_PALtemp13:
-      case ISA::IPR_PALtemp14:
-      case ISA::IPR_PALtemp15:
-      case ISA::IPR_PALtemp16:
-      case ISA::IPR_PALtemp17:
-      case ISA::IPR_PALtemp18:
-      case ISA::IPR_PALtemp19:
-      case ISA::IPR_PALtemp20:
-      case ISA::IPR_PALtemp21:
-      case ISA::IPR_PALtemp22:
-      case ISA::IPR_PAL_BASE:
-      case ISA::IPR_IC_PERR_STAT:
-      case ISA::IPR_DC_PERR_STAT:
-      case ISA::IPR_PMCTR:
+      case TheISA::IPR_PALtemp0:
+      case TheISA::IPR_PALtemp1:
+      case TheISA::IPR_PALtemp2:
+      case TheISA::IPR_PALtemp3:
+      case TheISA::IPR_PALtemp4:
+      case TheISA::IPR_PALtemp5:
+      case TheISA::IPR_PALtemp6:
+      case TheISA::IPR_PALtemp7:
+      case TheISA::IPR_PALtemp8:
+      case TheISA::IPR_PALtemp9:
+      case TheISA::IPR_PALtemp10:
+      case TheISA::IPR_PALtemp11:
+      case TheISA::IPR_PALtemp12:
+      case TheISA::IPR_PALtemp13:
+      case TheISA::IPR_PALtemp14:
+      case TheISA::IPR_PALtemp15:
+      case TheISA::IPR_PALtemp16:
+      case TheISA::IPR_PALtemp17:
+      case TheISA::IPR_PALtemp18:
+      case TheISA::IPR_PALtemp19:
+      case TheISA::IPR_PALtemp20:
+      case TheISA::IPR_PALtemp21:
+      case TheISA::IPR_PALtemp22:
+      case TheISA::IPR_PAL_BASE:
+      case TheISA::IPR_IC_PERR_STAT:
+      case TheISA::IPR_DC_PERR_STAT:
+      case TheISA::IPR_PMCTR:
         // write entire quad w/ no side-effect
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_CC_CTL:
+      case TheISA::IPR_CC_CTL:
         // This IPR resets the cycle counter.  We assume this only
         // happens once... let's verify that.
         assert(ipr[idx] == 0);
         ipr[idx] = 1;
         break;
 
-      case ISA::IPR_CC:
+      case TheISA::IPR_CC:
         // This IPR only writes the upper 64 bits.  It's ok to write
         // all 64 here since we mask out the lower 32 in rpcc (see
         // isa_desc).
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_PALtemp23:
+      case TheISA::IPR_PALtemp23:
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_PTE:
+      case TheISA::IPR_DTB_PTE:
         // write entire quad w/ no side-effect, tag is forthcoming
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_EXC_ADDR:
+      case TheISA::IPR_EXC_ADDR:
         // second least significant bit in PC is always zero
         ipr[idx] = val & ~2;
         break;
 
-      case ISA::IPR_ASTRR:
-      case ISA::IPR_ASTER:
+      case TheISA::IPR_ASTRR:
+      case TheISA::IPR_ASTER:
         // only write least significant four bits - privilege mask
         ipr[idx] = val & 0xf;
         break;
 
-      case ISA::IPR_IPLR:
+      case TheISA::IPR_IPLR:
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
         break;
 
-      case ISA::IPR_DTB_CM:
+      case TheISA::IPR_DTB_CM:
 
-      case ISA::IPR_ICM:
+      case TheISA::IPR_ICM:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_ALT_MODE:
+      case TheISA::IPR_ALT_MODE:
         // only write two mode bits - processor mode
         ipr[idx] = val & 0x18;
         break;
 
-      case ISA::IPR_MCSR:
+      case TheISA::IPR_MCSR:
         // more here after optimization...
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_SIRR:
+      case TheISA::IPR_SIRR:
         // only write software interrupt mask
         ipr[idx] = val & 0x7fff0;
         break;
 
-      case ISA::IPR_ICSR:
+      case TheISA::IPR_ICSR:
         ipr[idx] = val & ULL(0xffffff0300);
         break;
 
-      case ISA::IPR_IVPTBR:
-      case ISA::IPR_MVPTBR:
+      case TheISA::IPR_IVPTBR:
+      case TheISA::IPR_MVPTBR:
         ipr[idx] = val & ULL(0xffffffffc0000000);
         break;
 
-      case ISA::IPR_DC_TEST_CTL:
+      case TheISA::IPR_DC_TEST_CTL:
         ipr[idx] = val & 0x1ffb;
         break;
 
-      case ISA::IPR_DC_MODE:
-      case ISA::IPR_MAF_MODE:
+      case TheISA::IPR_DC_MODE:
+      case TheISA::IPR_MAF_MODE:
         ipr[idx] = val & 0x3f;
         break;
 
-      case ISA::IPR_ITB_ASN:
+      case TheISA::IPR_ITB_ASN:
         ipr[idx] = val & 0x7f0;
         break;
 
-      case ISA::IPR_DTB_ASN:
+      case TheISA::IPR_DTB_ASN:
         ipr[idx] = val & ULL(0xfe00000000000000);
         break;
 
-      case ISA::IPR_EXC_SUM:
-      case ISA::IPR_EXC_MASK:
+      case TheISA::IPR_EXC_SUM:
+      case TheISA::IPR_EXC_MASK:
         // any write to this register clears it
         ipr[idx] = 0;
         break;
 
-      case ISA::IPR_INTID:
-      case ISA::IPR_SL_RCV:
-      case ISA::IPR_MM_STAT:
-      case ISA::IPR_ITB_PTE_TEMP:
-      case ISA::IPR_DTB_PTE_TEMP:
+      case TheISA::IPR_INTID:
+      case TheISA::IPR_SL_RCV:
+      case TheISA::IPR_MM_STAT:
+      case TheISA::IPR_ITB_PTE_TEMP:
+      case TheISA::IPR_DTB_PTE_TEMP:
         // read-only registers
         return UnimplementedOpcodeFault;
 
-      case ISA::IPR_HWINT_CLR:
-      case ISA::IPR_SL_XMIT:
-      case ISA::IPR_DC_FLUSH:
-      case ISA::IPR_IC_FLUSH:
+      case TheISA::IPR_HWINT_CLR:
+      case TheISA::IPR_SL_XMIT:
+      case TheISA::IPR_DC_FLUSH:
+      case TheISA::IPR_IC_FLUSH:
         // the following are write only
         ipr[idx] = val;
         break;
 
-      case ISA::IPR_DTB_IA:
+      case TheISA::IPR_DTB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushAll();
         break;
 
-      case ISA::IPR_DTB_IAP:
+      case TheISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->dtb->flushProcesses();
         break;
 
-      case ISA::IPR_DTB_IS:
+      case TheISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]));
+        cpu->dtb->flushAddr(val, DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]));
         break;
 
-      case ISA::IPR_DTB_TAG: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_DTB_TAG: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
-          if (DTB_PTE_GH(ipr[ISA::IPR_DTB_PTE]) != 0)
+          if (DTB_PTE_GH(ipr[TheISA::IPR_DTB_PTE]) != 0)
               panic("PTE GH field != 0");
 
           // write entire quad
           ipr[idx] = val;
 
           // construct PTE for new entry
-          pte.ppn = DTB_PTE_PPN(ipr[ISA::IPR_DTB_PTE]);
-          pte.xre = DTB_PTE_XRE(ipr[ISA::IPR_DTB_PTE]);
-          pte.xwe = DTB_PTE_XWE(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonr = DTB_PTE_FONR(ipr[ISA::IPR_DTB_PTE]);
-          pte.fonw = DTB_PTE_FONW(ipr[ISA::IPR_DTB_PTE]);
-          pte.asma = DTB_PTE_ASMA(ipr[ISA::IPR_DTB_PTE]);
-          pte.asn = DTB_ASN_ASN(ipr[ISA::IPR_DTB_ASN]);
+          pte.ppn = DTB_PTE_PPN(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xre = DTB_PTE_XRE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.xwe = DTB_PTE_XWE(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonr = DTB_PTE_FONR(ipr[TheISA::IPR_DTB_PTE]);
+          pte.fonw = DTB_PTE_FONW(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asma = DTB_PTE_ASMA(ipr[TheISA::IPR_DTB_PTE]);
+          pte.asn = DTB_ASN_ASN(ipr[TheISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
           cpu->dtb->insert(val, pte);
       }
         break;
 
-      case ISA::IPR_ITB_PTE: {
-          struct ISA::PTE pte;
+      case TheISA::IPR_ITB_PTE: {
+          struct TheISA::PTE pte;
 
           // FIXME: granularity hints NYI...
           if (ITB_PTE_GH(val) != 0)
@@ -594,32 +598,32 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
           pte.fonr = ITB_PTE_FONR(val);
           pte.fonw = ITB_PTE_FONW(val);
           pte.asma = ITB_PTE_ASMA(val);
-          pte.asn = ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]);
+          pte.asn = ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          cpu->itb->insert(ipr[ISA::IPR_ITB_TAG], pte);
+          cpu->itb->insert(ipr[TheISA::IPR_ITB_TAG], pte);
       }
         break;
 
-      case ISA::IPR_ITB_IA:
+      case TheISA::IPR_ITB_IA:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushAll();
         break;
 
-      case ISA::IPR_ITB_IAP:
+      case TheISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
         cpu->itb->flushProcesses();
         break;
 
-      case ISA::IPR_ITB_IS:
+      case TheISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[ISA::IPR_ITB_ASN]));
+        cpu->itb->flushAddr(val, ITB_ASN_ASN(ipr[TheISA::IPR_ITB_ASN]));
         break;
 
       default: