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authorGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-19 02:34:52 -0500
commit0e4a80df1a471671b6ef7003e29124b6835ade42 (patch)
tree1d2c44d8c3462dd94c0fbf6e4f149e026c901aa8 /cpu/o3/rename.hh
parenta48c24b61eedf580645ff0294b225d1e69a9444b (diff)
parent463aa6d49d49ba9c383f07207df57bad75c58ec9 (diff)
downloadgem5-0e4a80df1a471671b6ef7003e29124b6835ade42.tar.xz
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch --HG-- extra : convert_revision : 090b30a7f70294e1aeb13ba0bc15da4061bdf348
Diffstat (limited to 'cpu/o3/rename.hh')
-rw-r--r--cpu/o3/rename.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh
index a17ec7311..9781480b6 100644
--- a/cpu/o3/rename.hh
+++ b/cpu/o3/rename.hh
@@ -46,7 +46,6 @@ class SimpleRename
{
public:
// Typedefs from the Impl.
- typedef typename Impl::ISA ISA;
typedef typename Impl::CPUPol CPUPol;
typedef typename Impl::DynInstPtr DynInstPtr;
typedef typename Impl::FullCPU FullCPU;
@@ -62,7 +61,8 @@ class SimpleRename
typedef typename CPUPol::RenameMap RenameMap;
// Typedefs from the ISA.
- typedef typename ISA::Addr Addr;
+ typedef TheISA::Addr Addr;
+ typedef TheISA::RegIndex RegIndex;
public:
// Rename will block if ROB becomes full or issue queue becomes full,