summaryrefslogtreecommitdiff
path: root/cpu/o3/rob_impl.hh
diff options
context:
space:
mode:
authorKevin Lim <ktlim@umich.edu>2006-05-04 11:36:20 -0400
committerKevin Lim <ktlim@umich.edu>2006-05-04 11:36:20 -0400
commitf3358e5f7b6452f14a6df5106129ef0cb2ed8b65 (patch)
tree284685f873ef56b9c9ae95131129c51193d3185f /cpu/o3/rob_impl.hh
parent4601230d35de7bbda5906d04a28e2387f0e5177b (diff)
downloadgem5-f3358e5f7b6452f14a6df5106129ef0cb2ed8b65.tar.xz
O3 CPU now handles being used with the sampler.
cpu/o3/2bit_local_pred.cc: cpu/o3/2bit_local_pred.hh: cpu/o3/bpred_unit.hh: cpu/o3/bpred_unit_impl.hh: cpu/o3/btb.cc: cpu/o3/btb.hh: cpu/o3/commit.hh: cpu/o3/commit_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/o3/decode.hh: cpu/o3/decode_impl.hh: cpu/o3/fetch.hh: cpu/o3/fetch_impl.hh: cpu/o3/fu_pool.cc: cpu/o3/fu_pool.hh: cpu/o3/iew.hh: cpu/o3/iew_impl.hh: cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: cpu/o3/lsq.hh: cpu/o3/lsq_impl.hh: cpu/o3/lsq_unit.hh: cpu/o3/lsq_unit_impl.hh: cpu/o3/mem_dep_unit.hh: cpu/o3/mem_dep_unit_impl.hh: cpu/o3/ras.cc: cpu/o3/ras.hh: cpu/o3/rename.hh: cpu/o3/rename_impl.hh: cpu/o3/rob.hh: cpu/o3/rob_impl.hh: cpu/o3/sat_counter.cc: cpu/o3/sat_counter.hh: cpu/o3/thread_state.hh: Handle switching out and taking over. Needs to be able to reset all state. cpu/o3/alpha_cpu_impl.hh: Handle taking over from another XC. --HG-- extra : convert_revision : b936e826f0f8a18319bfa940ff35097b4192b449
Diffstat (limited to 'cpu/o3/rob_impl.hh')
-rw-r--r--cpu/o3/rob_impl.hh25
1 files changed, 25 insertions, 0 deletions
diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh
index 96d907cda..02a4bfbee 100644
--- a/cpu/o3/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -121,6 +121,31 @@ ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
activeThreads = at_ptr;
}
+template <class Impl>
+void
+ROB<Impl>::switchOut()
+{
+ for (int tid = 0; tid < numThreads; tid++) {
+ instList[tid].clear();
+ }
+}
+
+template <class Impl>
+void
+ROB<Impl>::takeOverFrom()
+{
+ for (int tid=0; tid < numThreads; tid++) {
+ doneSquashing[tid] = true;
+ threadEntries[tid] = 0;
+ squashIt[tid] = instList[tid].end();
+ }
+ numInstsInROB = 0;
+
+ // Initialize the "universal" ROB head & tail point to invalid
+ // pointers
+ head = instList[0].end();
+ tail = instList[0].end();
+}
template <class Impl>
void