Build options are set via a build_options file in the

build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.  Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.

SConscript:
    MySQL detection moved to SConstruct.
    Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
    Convert compile flags from def/undef to 0/1.
    Set via #include config/*.hh instead of command line.
    Revamp fenv.h support... most of the ugliness is hidden
    in base/fenv.hh now.
base/mysql.hh:
    Fix typo in #ifndef guard.
build/SConstruct:
    Build options are set via a build_options file in the
    build directory instead of being inferred from the name
    of the build directory.
    Options are passed to C++ via config/*.hh files instead of
    via the command line.
python/SConscript:
    Generate m5_build_env directly from scons options
    instead of indirectly via CPPDEFINES.
python/m5/convert.py:
    Allow '0' and '1' for booleans.
    Rewrite toBool to use dict.
base/fenv.hh:
    Revamp <fenv.h> support to make it a compile option
    (so we can test w/o it even if it's present) and to
    make isa_desc cleaner.

--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad

15 files changed, 52 insertions, 45 deletions

diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 545165b2b..cba57d189 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -44,7 +44,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     AlphaFullCPU(Params &params);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb;
     AlphaDTB *dtb;
 #endif
@@ -52,7 +52,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   public:
     void regStats();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     //Note that the interrupt stuff from the base CPU might be somewhat
     //ISA specific (ie NumInterruptLevels).  These functions might not
     //be needed in FullCPU though.
@@ -131,7 +131,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     // Most of the full system code and syscall emulation is not yet
     // implemented.  These functions do show what the final interface will
     // look like.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t *getIpr();
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
@@ -149,7 +149,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
 #endif
 
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     // Need to change these into regfile calls that directly set a certain
     // register.  Actually, these functions should handle most of this
     // functionality by themselves; should look up the rename and then
@@ -191,7 +191,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     void copyFromXC();
 
   public:
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     bool palShadowEnabled;
 
     // Not sure this is used anywhere.
@@ -210,7 +210,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
         if (req->flags & LOCKED) {
             MiscRegFile *cregs = &req->xc->regs.miscRegs;
             cregs->lock_addr = req->paddr;
@@ -233,7 +233,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
+#if FULL_SYSTEM && defined(TARGET_ALPHA)
 
         MiscRegFile *cregs;
 
diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc
index 57c567471..3547fb1b5 100644
--- a/cpu/o3/alpha_cpu_builder.cc
+++ b/cpu/o3/alpha_cpu_builder.cc
@@ -45,7 +45,7 @@
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "base/remote_gdb.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
@@ -69,7 +69,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     Param<int> clock;
     Param<int> numThreads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 SimObjectParam<System *> system;
 Param<int> cpu_id;
 SimObjectParam<AlphaITB *> itb;
@@ -162,7 +162,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
     INIT_PARAM(clock, "clock speed"),
     INIT_PARAM(numThreads, "number of HW thread contexts"),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     INIT_PARAM(system, "System object"),
     INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(itb, "Instruction translation buffer"),
@@ -273,7 +273,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
 {
     DerivAlphaFullCPU *cpu;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
 #else
@@ -295,7 +295,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     params.name = getInstanceName();
     params.numberOfThreads = actual_num_threads;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     params.system = system;
     params.cpu_id = cpu_id;
     params.itb = itb;
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 146186e2f..2a764740b 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -39,7 +39,7 @@
 #include "cpu/o3/alpha_params.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/isa_traits.hh"
 //#include "arch/alpha/ev5.hh"
@@ -75,7 +75,7 @@ AlphaFullCPU<Impl>::regStats()
     this->commit.regStats();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 
 // Will probably need to know which thread is calling syscall
 // Will need to pass that information in to the DynInst when it is constructed,
@@ -238,7 +238,7 @@ AlphaFullCPU<Impl>::copyFromXC()
     this->funcExeInst = this->xc->func_exe_inst;
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 template <class Impl>
 uint64_t *
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index 8a9a681d2..bb90bf21a 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
     uint64_t readFpcr();
     void setFpcr(uint64_t val);
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     Fault hwrei();
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 437b113e4..d1ebb812d 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -95,7 +95,7 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
     this->cpu->setFpcr(val);
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 template <class Impl>
 uint64_t
 AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
diff --git a/cpu/o3/alpha_params.hh b/cpu/o3/alpha_params.hh
index 77e6f3649..79b0937e3 100644
--- a/cpu/o3/alpha_params.hh
+++ b/cpu/o3/alpha_params.hh
@@ -49,7 +49,7 @@ class AlphaSimpleParams : public BaseFullCPU::Params
 {
   public:
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     AlphaITB *itb; AlphaDTB *dtb;
 #else
     std::vector<Process *> workload;
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index ac3d83174..dc0986772 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -186,7 +186,7 @@ SimpleCommit<Impl>::commit()
     // in the IPR.  Look at IPR[EXC_ADDR];
     // hwrei() is what resets the PC to the place where instruction execution
     // beings again.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     if (//checkInterrupts &&
         cpu->check_interrupts() &&
         !cpu->inPalMode(readCommitPC())) {
@@ -397,7 +397,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
 
     if (inst_fault != No_Fault && inst_fault != Fake_Mem_Fault) {
         if (!head_inst->isNop()) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
             cpu->trap(inst_fault);
 #else // !FULL_SYSTEM
             panic("fault (%d) detected @ PC %08p", inst_fault,
diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc
index b447439c0..adc7b6bbc 100644
--- a/cpu/o3/cpu.cc
+++ b/cpu/o3/cpu.cc
@@ -26,7 +26,9 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifdef FULL_SYSTEM
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
 #include "sim/system.hh"
 #else
 #include "sim/process.hh"
@@ -68,7 +70,7 @@ FullO3CPU<Impl>::TickEvent::description()
 //Call constructor to all the pipeline stages here
 template <class Impl>
 FullO3CPU<Impl>::FullO3CPU(Params &params)
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     : BaseFullCPU(params),
 #else
     : BaseFullCPU(params),
@@ -105,7 +107,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
       globalSeqNum(1),
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
       system(params.system),
       memCtrl(system->memctrl),
       physmem(system->physmem),
@@ -125,12 +127,12 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 {
     _status = Idle;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     thread.resize(this->number_of_threads);
 #endif
 
     for (int i = 0; i < this->number_of_threads; ++i) {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         assert(i == 0);
         system->execContexts[i] =
             new ExecContext(this, i, system, itb, dtb, mem);
@@ -153,7 +155,7 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
 
     // Note that this is a hack so that my code which still uses xc-> will
     // still work.  I should remove this eventually
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     xc = system->execContexts[0];
 #else
     xc = thread[0];
@@ -246,7 +248,7 @@ FullO3CPU<Impl>::init()
 
         // Need to do a copy of the xc->regs into the CPU's regfile so
         // that it can start properly.
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         ExecContext *src_xc = system->execContexts[0];
 #else
         ExecContext *src_xc = thread[0];
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 10f60b5da..75dca5056 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -42,13 +42,14 @@
 
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
+#include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/cpu_policy.hh"
 #include "cpu/exec_context.hh"
 #include "sim/process.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 using namespace EV5;
 #endif
@@ -62,7 +63,7 @@ class BaseFullCPU : public BaseCPU
   public:
     typedef BaseCPU::Params Params;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     BaseFullCPU(Params &params);
 #else
     BaseFullCPU(Params &params);
@@ -143,7 +144,7 @@ class FullO3CPU : public BaseFullCPU
     /** Get the current instruction sequence number, and increment it. */
     InstSeqNum getAndIncrementInstSeq();
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     /** Check if this address is a valid instruction address. */
     bool validInstAddr(Addr addr) { return true; }
 
@@ -325,7 +326,7 @@ class FullO3CPU : public BaseFullCPU
     /** Temporary function to get pointer to exec context. */
     ExecContext *xcBase()
     {
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
         return system->execContexts[0];
 #else
         return thread[0];
@@ -334,7 +335,7 @@ class FullO3CPU : public BaseFullCPU
 
     InstSeqNum globalSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     System *system;
 
     MemoryController *memCtrl;
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index 75b6abb3d..c943fd36a 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -80,7 +80,7 @@ SimpleFetch<Impl>::SimpleFetch(Params &params)
     memReq = new MemReq();
     // Not sure of this parameter.  I think it should be based on the
     // thread number.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
     memReq->asid = 0;
 #else
     memReq->asid = 0;
@@ -229,7 +229,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
     // of the instructions in the cache line until either the end of the
     // cache line or a predicted taken branch is encountered.
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     // Flag to say whether or not address is physical addr.
     unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
 #else
@@ -605,7 +605,7 @@ SimpleFetch<Impl>::fetch()
         DPRINTF(Fetch, "Fetch: Blocked, need to handle the trap.\n");
 
         _status = Blocked;
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 //        cpu->trap(fault);
         // Send a signal to the ROB indicating that there's a trap from the
         // fetch stage that needs to be handled.  Need to indicate that
diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh
index 69cd3799a..af23c6f45 100644
--- a/cpu/o3/iew.hh
+++ b/cpu/o3/iew.hh
@@ -35,6 +35,7 @@
 
 #include <queue>
 
+#include "config/full_system.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "cpu/o3/comm.hh"
@@ -169,7 +170,7 @@ class SimpleIEW
 
     LDSTQ ldstQueue;
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
   public:
     void lsqWriteback();
 #endif
diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh
index 5f0d7b647..b8a2b4dc9 100644
--- a/cpu/o3/iew_impl.hh
+++ b/cpu/o3/iew_impl.hh
@@ -726,7 +726,7 @@ SimpleIEW<Impl>::iew()
     issueToExecQueue.advance();
 }
 
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 template<class Impl>
 void
 SimpleIEW<Impl>::lsqWriteback()
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index e63b7fcfb..4d47b8f9c 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -33,9 +33,10 @@
 
 #include "arch/alpha/isa_traits.hh"
 #include "base/trace.hh"
+#include "config/full_system.hh"
 #include "cpu/o3/comm.hh"
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 #include "arch/alpha/ev5.hh"
 #include "kern/kernel_stats.hh"
 
@@ -209,7 +210,7 @@ class PhysRegFile
         miscRegs.fpcr = val;
     }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     uint64_t readIpr(int idx, Fault &fault);
     Fault setIpr(int idx, uint64_t val);
     InternalProcReg *getIpr() { return ipr; }
@@ -235,7 +236,7 @@ class PhysRegFile
     /** Next-cycle program counter. */
     Addr npc;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
     IntReg palregs[NumIntRegs];	// PAL shadow registers
@@ -267,7 +268,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
     memset(floatRegFile, 0, sizeof(*floatRegFile));
 }
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
 
 //Problem:  This code doesn't make sense at the RegFile level because it
 //needs things such as the itb and dtb.  Either put it at the CPU level or
@@ -629,6 +630,6 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
     return No_Fault;
 }
 
-#endif // #ifdef FULL_SYSTEM
+#endif // #if FULL_SYSTEM
 
 #endif // __CPU_O3_CPU_REGFILE_HH__
diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh
index 5fd62e911..2068b36ab 100644
--- a/cpu/o3/rename_impl.hh
+++ b/cpu/o3/rename_impl.hh
@@ -28,6 +28,7 @@
 
 #include <list>
 
+#include "config/full_system.hh"
 #include "cpu/o3/rename.hh"
 
 template <class Impl>
@@ -232,7 +233,7 @@ SimpleRename<Impl>::doSquash()
 
     InstSeqNum squashed_seq_num = fromCommit->commitInfo.doneSeqNum;
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
     assert(!historyBuffer.empty());
 #else
     // After a syscall squashes everything, the history buffer may be empty
@@ -543,7 +544,7 @@ SimpleRename<Impl>::tick()
 
     // Ugly code, revamp all of the tick() functions eventually.
     if (fromCommit->commitInfo.doneSeqNum != 0 && _status != Squashing) {
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (!fromCommit->commitInfo.squash) {
             removeFromHistory(fromCommit->commitInfo.doneSeqNum);
         }
diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh
index 51f4afe75..e7a5671d9 100644
--- a/cpu/o3/rob_impl.hh
+++ b/cpu/o3/rob_impl.hh
@@ -29,6 +29,7 @@
 #ifndef __CPU_O3_CPU_ROB_IMPL_HH__
 #define __CPU_O3_CPU_ROB_IMPL_HH__
 
+#include "config/full_system.hh"
 #include "cpu/o3/rob.hh"
 
 template <class Impl>
@@ -209,7 +210,7 @@ ROB<Impl>::doSquash()
         // will never be false.  Normally the squash would never be able
         // to go past the head of the ROB; in this case it might, so it
         // must be handled otherwise it will segfault.
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
         if (squashIt == cpu->instList.begin()) {
             DPRINTF(ROB, "ROB: Reached head of instruction list while "
                     "squashing.\n");