diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 03:38:21 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-21 03:38:21 -0500 |
commit | 3f7979c99d8dc4f434e3daa2e179616f1669e16e (patch) | |
tree | 85d426effe10c1b34a3f434417213231a4aac528 /cpu/o3 | |
parent | 74d7cd1ceadd8ba803bbb83750e11a3c488d3fe1 (diff) | |
download | gem5-3f7979c99d8dc4f434e3daa2e179616f1669e16e.tar.xz |
Made Addr a global type
--HG--
extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
Diffstat (limited to 'cpu/o3')
-rw-r--r-- | cpu/o3/2bit_local_pred.hh | 2 | ||||
-rw-r--r-- | cpu/o3/alpha_cpu.hh | 1 | ||||
-rw-r--r-- | cpu/o3/alpha_dyn_inst.hh | 2 | ||||
-rw-r--r-- | cpu/o3/bpred_unit.hh | 2 | ||||
-rw-r--r-- | cpu/o3/btb.hh | 2 | ||||
-rw-r--r-- | cpu/o3/decode.hh | 3 | ||||
-rw-r--r-- | cpu/o3/fetch.hh | 1 | ||||
-rw-r--r-- | cpu/o3/ras.hh | 2 | ||||
-rw-r--r-- | cpu/o3/regfile.hh | 1 | ||||
-rw-r--r-- | cpu/o3/rename.hh | 1 | ||||
-rw-r--r-- | cpu/o3/store_set.hh | 2 | ||||
-rw-r--r-- | cpu/o3/tournament_pred.hh | 2 |
12 files changed, 0 insertions, 21 deletions
diff --git a/cpu/o3/2bit_local_pred.hh b/cpu/o3/2bit_local_pred.hh index 78efe1e43..97433e542 100644 --- a/cpu/o3/2bit_local_pred.hh +++ b/cpu/o3/2bit_local_pred.hh @@ -35,8 +35,6 @@ class DefaultBP { - protected: - typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index bf3556b8e..2be70f5c2 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -40,7 +40,6 @@ template <class Impl> class AlphaFullCPU : public FullO3CPU<Impl> { protected: - typedef AlphaISA::Addr Addr; typedef TheISA::IntReg IntReg; public: typedef typename Impl::Params Params; diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh index 22be2aae5..b113d9487 100644 --- a/cpu/o3/alpha_dyn_inst.hh +++ b/cpu/o3/alpha_dyn_inst.hh @@ -50,8 +50,6 @@ class AlphaDynInst : public BaseDynInst<Impl> /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; - /** Memory address type. */ - typedef TheISA::Addr Addr; /** Logical register index type. */ typedef TheISA::RegIndex RegIndex; /** Integer register index type. */ diff --git a/cpu/o3/bpred_unit.hh b/cpu/o3/bpred_unit.hh index c874f9e04..0a77b83dc 100644 --- a/cpu/o3/bpred_unit.hh +++ b/cpu/o3/bpred_unit.hh @@ -53,8 +53,6 @@ template<class Impl> class TwobitBPredUnit { - protected: - typedef TheISA::Addr Addr; public: typedef typename Impl::Params Params; typedef typename Impl::DynInstPtr DynInstPtr; diff --git a/cpu/o3/btb.hh b/cpu/o3/btb.hh index f443ddbaf..77bdc32ea 100644 --- a/cpu/o3/btb.hh +++ b/cpu/o3/btb.hh @@ -34,8 +34,6 @@ class DefaultBTB { - protected: - typedef TheISA::Addr Addr; private: struct BTBEntry { diff --git a/cpu/o3/decode.hh b/cpu/o3/decode.hh index bae9a7015..5b9a0f822 100644 --- a/cpu/o3/decode.hh +++ b/cpu/o3/decode.hh @@ -49,9 +49,6 @@ class SimpleDecode typedef typename CPUPol::DecodeStruct DecodeStruct; typedef typename CPUPol::TimeStruct TimeStruct; - // Typedefs from the ISA. - typedef TheISA::Addr Addr; - public: // The only time decode will become blocked is if dispatch becomes // blocked, which means IQ or ROB is probably full. diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index e4d374c1d..82a6cd818 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -61,7 +61,6 @@ class SimpleFetch /** Typedefs from ISA. */ typedef TheISA::MachInst MachInst; - typedef TheISA::Addr Addr; public: enum Status { diff --git a/cpu/o3/ras.hh b/cpu/o3/ras.hh index fd7f5fe1c..46d98181e 100644 --- a/cpu/o3/ras.hh +++ b/cpu/o3/ras.hh @@ -34,8 +34,6 @@ class ReturnAddrStack { - protected: - typedef TheISA::Addr Addr; public: ReturnAddrStack(unsigned numEntries); diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index 655a3cad9..021f9b0b6 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -53,7 +53,6 @@ template <class Impl> class PhysRegFile { protected: - typedef TheISA::Addr Addr; typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::MiscRegFile MiscRegFile; diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index 9781480b6..07b442964 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -61,7 +61,6 @@ class SimpleRename typedef typename CPUPol::RenameMap RenameMap; // Typedefs from the ISA. - typedef TheISA::Addr Addr; typedef TheISA::RegIndex RegIndex; public: diff --git a/cpu/o3/store_set.hh b/cpu/o3/store_set.hh index c67d30fcb..5a885d838 100644 --- a/cpu/o3/store_set.hh +++ b/cpu/o3/store_set.hh @@ -36,8 +36,6 @@ class StoreSet { - protected: - typedef TheISA::Addr Addr; public: typedef unsigned SSID; diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index 6cfd24cfb..cb93c2f67 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -35,8 +35,6 @@ class TournamentBP { - protected: - typedef TheISA::Addr Addr; public: /** * Default branch predictor constructor. |