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authorGabe Black <gblack@eecs.umich.edu>2006-03-07 14:08:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-03-07 14:08:01 -0500
commit8106a804508a42455650082a83f4cdb366ca5148 (patch)
treebfe97803535239ff9665fc1e6c278893df832ac7 /cpu/o3
parentcd62fed1a7c535befaa00c8775de78f9f29b1274 (diff)
downloadgem5-8106a804508a42455650082a83f4cdb366ca5148.tar.xz
Pushed ev5.hh out of the non-alpha code.
arch/SConscript: ev5 should now be contained within alpha specific code. arch/alpha/ev5.cc: arch/alpha/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. arch/sparc/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes. cpu/o3/alpha_cpu.hh: Added typedefs which are required now that there isn't a using namespace EV5. cpu/o3/alpha_cpu_impl.hh: Some small changes so that ev5.hh isn't needed directly. cpu/o3/cpu.hh: Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile. cpu/o3/regfile.hh: Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array. --HG-- extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
Diffstat (limited to 'cpu/o3')
-rw-r--r--cpu/o3/alpha_cpu.hh2
-rw-r--r--cpu/o3/alpha_cpu_impl.hh3
-rw-r--r--cpu/o3/cpu.hh9
-rw-r--r--cpu/o3/regfile.hh3
4 files changed, 6 insertions, 11 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 38c00a3a9..55fde1f1d 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -42,6 +42,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
protected:
typedef TheISA::IntReg IntReg;
typedef TheISA::MiscReg MiscReg;
+ typedef TheISA::RegFile RegFile;
+ typedef TheISA::MiscRegFile MiscRegFile;
public:
typedef typename Impl::Params Params;
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index a1c659b51..5ab9e6e75 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arch/alpha/faults.hh"
#include "base/cprintf.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
@@ -257,7 +258,7 @@ Fault
AlphaFullCPU<Impl>::hwrei()
{
if (!inPalMode())
- return new UnimplementedOpcodeFault;
+ return new AlphaISA::UnimplementedOpcodeFault;
this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 02908887e..31a1b604b 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -49,11 +49,6 @@
#include "cpu/exec_context.hh"
#include "sim/process.hh"
-#if FULL_SYSTEM
-#include "arch/ev5.hh"
-using namespace EV5;
-#endif
-
class FunctionalMemory;
class Process;
@@ -152,11 +147,11 @@ class FullO3CPU : public BaseFullCPU
/** Get instruction asid. */
int getInstAsid()
- { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
+ { return regFile.miscRegs.getInstAsid(); }
/** Get data asid. */
int getDataAsid()
- { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
+ { return regFile.miscRegs.getDataAsid(); }
#else
bool validInstAddr(Addr addr)
{ return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 03ad2da46..1e6e10f29 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -38,10 +38,8 @@
#include "cpu/o3/comm.hh"
#if FULL_SYSTEM
-#include "arch/ev5.hh"
#include "kern/kernel_stats.hh"
-using namespace EV5;
#endif
// This really only depends on the ISA, and not the Impl. It might be nicer
@@ -237,7 +235,6 @@ class PhysRegFile
private:
// This is ISA specifc stuff; remove it eventually once ISAImpl is used
// IntReg palregs[NumIntRegs]; // PAL shadow registers
- InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
int intrflag; // interrupt flag
bool pal_shadow; // using pal_shadow registers
#endif