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authorGabe Black <gblack@eecs.umich.edu>2006-02-24 01:51:45 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-24 01:51:45 -0500
commit08637efadc40a1003d68bba91dedb007fe10798c (patch)
tree49405fe5d18c7e120d926b4b95f4aeeda3ef9097 /cpu/o3
parenta5f8392d343d0799d6c7f687ab3d342709717510 (diff)
downloadgem5-08637efadc40a1003d68bba91dedb007fe10798c.tar.xz
Changed Fault from a FaultBase * to a RefCountingPtr, added "new"s where appropriate, and took away the constant examples of each fault which where for comparing to a fault to determine its type.
arch/alpha/alpha_memory.cc: arch/alpha/isa/decoder.isa: Added news where faults are created. arch/alpha/ev5.cc: Changed places where a fault was compared to a fault type to use isA rather than == arch/alpha/faults.cc: arch/alpha/faults.hh: Changed Fault to be a RefCountingPtr arch/alpha/isa/fp.isa: Added a new where a FloatEnableFault was created. arch/alpha/isa/unimp.isa: arch/alpha/isa/unknown.isa: Added a new where an UnimplementedFault is created. base/refcnt.hh: Added include of stddef.h for the NULL macro cpu/base_dyn_inst.cc: Added a new where an UnimplementedOpcodeFault is created. cpu/o3/alpha_cpu_impl.hh: Changed places where a fault was compared to a fault type to use isA rather than ==. Also changed fault->name to fault->name() cpu/o3/regfile.hh: Added new where UnimplementedOpcodeFaults are created. cpu/simple/cpu.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Also added a new where an Interrupt fault is created. dev/alpha_console.cc: Added news where MachineCheckFaults are created. dev/pcidev.hh: Added news where MachineCheckFaults are generated. dev/sinic.cc: Changed places where a fault was compared to a fault type to use isA rather than ==. Added news where MachineCheckFaults are created. Fixed a problem where m5.fast had unused variables. kern/kernel_stats.cc: Commented out where _faults is initialized. This statistic will probably be moved elsewhere in the future. kern/kernel_stats.hh: Commented out the declaration of _fault. when fault() is called, the fault increments its own stat. sim/faults.cc: sim/faults.hh: Changed Fault from a FaultBase * to a RefCountingPtr. --HG-- extra : convert_revision : b40ccfc42482d5a115e111dd897fa378d23c6c7d
Diffstat (limited to 'cpu/o3')
-rw-r--r--cpu/o3/alpha_cpu_impl.hh14
-rw-r--r--cpu/o3/regfile.hh8
2 files changed, 11 insertions, 11 deletions
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 7ec1ba663..c0ec1fb33 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -280,7 +280,7 @@ AlphaFullCPU<Impl>::hwrei()
uint64_t *ipr = getIpr();
if (!inPalMode())
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
this->setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
@@ -329,21 +329,21 @@ AlphaFullCPU<Impl>::trap(Fault fault)
// miss
uint64_t PC = this->commit.readCommitPC();
- DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
- this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
+ DPRINTF(Fault, "Fault %s\n", fault->name());
+ this->recordEvent(csprintf("Fault %s", fault->name()));
-// kernelStats.fault(fault);
+ //kernelStats.fault(fault);
- if (fault == ArithmeticFault)
+ if (fault->isA<ArithmeticFault>())
panic("Arithmetic traps are unimplemented!");
AlphaISA::InternalProcReg *ipr = getIpr();
// exception restart address - Get the commit PC
- if (fault != InterruptFault || !inPalMode(PC))
+ if (!fault->isA<InterruptFault>() || !inPalMode(PC))
ipr[AlphaISA::IPR_EXC_ADDR] = PC;
- if (fault == PalFault || fault == ArithmeticFault /* ||
+ if (fault->isA<PalFault>() || fault->isA<ArithmeticFault>() /* ||
fault == InterruptFault && !PC_PAL(regs.pc) */) {
// traps... skip faulting instruction
ipr[AlphaISA::IPR_EXC_ADDR] += 4;
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index ee7b8858e..7e36a6ead 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -372,12 +372,12 @@ PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
case TheISA::IPR_DTB_IAP:
case TheISA::IPR_ITB_IA:
case TheISA::IPR_ITB_IAP:
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
default:
// invalid IPR
- fault = UnimplementedOpcodeFault;
+ fault = new UnimplementedOpcodeFault;
break;
}
@@ -525,7 +525,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
case TheISA::IPR_ITB_PTE_TEMP:
case TheISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
case TheISA::IPR_HWINT_CLR:
case TheISA::IPR_SL_XMIT:
@@ -627,7 +627,7 @@ PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
default:
// invalid IPR
- return UnimplementedOpcodeFault;
+ return new UnimplementedOpcodeFault;
}
// no error...