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authorGabe Black <gblack@eecs.umich.edu>2006-02-21 20:10:40 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-21 20:10:40 -0500
commit8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d (patch)
treeaa785d4b846823e1960c7b308e6de1c90cf6fb3f /cpu/o3
parent3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff)
downloadgem5-8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d.tar.xz
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
Diffstat (limited to 'cpu/o3')
-rw-r--r--cpu/o3/alpha_cpu.hh34
-rw-r--r--cpu/o3/alpha_cpu_impl.hh8
-rw-r--r--cpu/o3/alpha_dyn_inst.hh14
-rw-r--r--cpu/o3/alpha_dyn_inst_impl.hh8
-rw-r--r--cpu/o3/commit_impl.hh2
-rw-r--r--cpu/o3/fetch.hh2
-rw-r--r--cpu/o3/fetch_impl.hh6
-rw-r--r--cpu/o3/regfile.hh8
8 files changed, 41 insertions, 41 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 2be70f5c2..b35bcf9e3 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -63,23 +63,23 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// void clear_interrupt(int int_num, int index);
// void clear_interrupts();
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return itb->translate(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dtb->translate(req, false);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dtb->translate(req, true);
}
#else
- Fault * dummyTranslation(MemReqPtr &req)
+ Fault dummyTranslation(MemReqPtr &req)
{
#if 0
assert((req->vaddr >> 48 & 0xffff) == 0);
@@ -91,17 +91,17 @@ class AlphaFullCPU : public FullO3CPU<Impl>
return NoFault;
}
- Fault * translateInstReq(MemReqPtr &req)
+ Fault translateInstReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataReadReq(MemReqPtr &req)
+ Fault translateDataReadReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
- Fault * translateDataWriteReq(MemReqPtr &req)
+ Fault translateDataWriteReq(MemReqPtr &req)
{
return dummyTranslation(req);
}
@@ -136,16 +136,16 @@ class AlphaFullCPU : public FullO3CPU<Impl>
// look like.
#if FULL_SYSTEM
uint64_t *getIpr();
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
int readIntrFlag();
void setIntrFlag(int val);
- Fault * hwrei();
+ Fault hwrei();
bool inPalMode() { return AlphaISA::PcPAL(this->regFile.readPC()); }
bool inPalMode(uint64_t PC)
{ return AlphaISA::PcPAL(PC); }
- void trap(Fault * fault);
+ void trap(Fault fault);
bool simPalCheck(int palFunc);
void processInterrupts();
@@ -198,7 +198,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
bool palShadowEnabled;
// Not sure this is used anywhere.
- void intr_post(RegFile *regs, Fault * fault, Addr pc);
+ void intr_post(RegFile *regs, Fault fault, Addr pc);
// Actually used within exec files. Implement properly.
void swapPALShadow(bool use_shadow);
// Called by CPU constructor. Can implement as I please.
@@ -211,7 +211,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
template <class T>
- Fault * read(MemReqPtr &req, T &data)
+ Fault read(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
if (req->flags & LOCKED) {
@@ -221,20 +221,20 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
#endif
- Fault * error;
+ Fault error;
error = this->mem->read(req, data);
data = gtoh(data);
return error;
}
template <class T>
- Fault * read(MemReqPtr &req, T &data, int load_idx)
+ Fault read(MemReqPtr &req, T &data, int load_idx)
{
return this->iew.ldstQueue.read(req, data, load_idx);
}
template <class T>
- Fault * write(MemReqPtr &req, T &data)
+ Fault write(MemReqPtr &req, T &data)
{
#if FULL_SYSTEM && defined(TARGET_ALPHA)
@@ -284,7 +284,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
}
template <class T>
- Fault * write(MemReqPtr &req, T &data, int store_idx)
+ Fault write(MemReqPtr &req, T &data, int store_idx)
{
return this->iew.ldstQueue.write(req, data, store_idx);
}
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 6736cf9bc..7ec1ba663 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -246,13 +246,13 @@ AlphaFullCPU<Impl>::getIpr()
template <class Impl>
uint64_t
-AlphaFullCPU<Impl>::readIpr(int idx, Fault * &fault)
+AlphaFullCPU<Impl>::readIpr(int idx, Fault &fault)
{
return this->regFile.readIpr(idx, fault);
}
template <class Impl>
-Fault *
+Fault
AlphaFullCPU<Impl>::setIpr(int idx, uint64_t val)
{
return this->regFile.setIpr(idx, val);
@@ -274,7 +274,7 @@ AlphaFullCPU<Impl>::setIntrFlag(int val)
// Can force commit stage to squash and stuff.
template <class Impl>
-Fault *
+Fault
AlphaFullCPU<Impl>::hwrei()
{
uint64_t *ipr = getIpr();
@@ -323,7 +323,7 @@ AlphaFullCPU<Impl>::simPalCheck(int palFunc)
// stage.
template <class Impl>
void
-AlphaFullCPU<Impl>::trap(Fault * fault)
+AlphaFullCPU<Impl>::trap(Fault fault)
{
// Keep in mind that a trap may be initiated by fetch if there's a TLB
// miss
diff --git a/cpu/o3/alpha_dyn_inst.hh b/cpu/o3/alpha_dyn_inst.hh
index b113d9487..f282c287c 100644
--- a/cpu/o3/alpha_dyn_inst.hh
+++ b/cpu/o3/alpha_dyn_inst.hh
@@ -69,7 +69,7 @@ class AlphaDynInst : public BaseDynInst<Impl>
AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
- Fault * execute()
+ Fault execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
@@ -82,13 +82,13 @@ class AlphaDynInst : public BaseDynInst<Impl>
void setFpcr(uint64_t val);
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
- Fault * hwrei();
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
+ Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
- void trap(Fault * fault);
+ void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
void syscall();
@@ -215,12 +215,12 @@ class AlphaDynInst : public BaseDynInst<Impl>
}
public:
- Fault * calcEA()
+ Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
- Fault * memAccess()
+ Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
diff --git a/cpu/o3/alpha_dyn_inst_impl.hh b/cpu/o3/alpha_dyn_inst_impl.hh
index 9f9df3da1..eebe7675a 100644
--- a/cpu/o3/alpha_dyn_inst_impl.hh
+++ b/cpu/o3/alpha_dyn_inst_impl.hh
@@ -98,20 +98,20 @@ AlphaDynInst<Impl>::setFpcr(uint64_t val)
#if FULL_SYSTEM
template <class Impl>
uint64_t
-AlphaDynInst<Impl>::readIpr(int idx, Fault * &fault)
+AlphaDynInst<Impl>::readIpr(int idx, Fault &fault)
{
return this->cpu->readIpr(idx, fault);
}
template <class Impl>
-Fault *
+Fault
AlphaDynInst<Impl>::setIpr(int idx, uint64_t val)
{
return this->cpu->setIpr(idx, val);
}
template <class Impl>
-Fault *
+Fault
AlphaDynInst<Impl>::hwrei()
{
return this->cpu->hwrei();
@@ -140,7 +140,7 @@ AlphaDynInst<Impl>::inPalMode()
template <class Impl>
void
-AlphaDynInst<Impl>::trap(Fault * fault)
+AlphaDynInst<Impl>::trap(Fault fault)
{
this->cpu->trap(fault);
}
diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh
index 47b4dfd00..e289bc0c0 100644
--- a/cpu/o3/commit_impl.hh
+++ b/cpu/o3/commit_impl.hh
@@ -393,7 +393,7 @@ SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
}
// Check if the instruction caused a fault. If so, trap.
- Fault * inst_fault = head_inst->getFault();
+ Fault inst_fault = head_inst->getFault();
if (inst_fault != NoFault) {
if (!head_inst->isNop()) {
diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh
index 82a6cd818..cc64800d9 100644
--- a/cpu/o3/fetch.hh
+++ b/cpu/o3/fetch.hh
@@ -122,7 +122,7 @@ class SimpleFetch
* @param fetch_PC The PC address that is being fetched from.
* @return Any fault that occured.
*/
- Fault * fetchCacheLine(Addr fetch_PC);
+ Fault fetchCacheLine(Addr fetch_PC);
inline void doSquash(const Addr &new_PC);
diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh
index e8d333ed4..8029fc732 100644
--- a/cpu/o3/fetch_impl.hh
+++ b/cpu/o3/fetch_impl.hh
@@ -221,7 +221,7 @@ SimpleFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC)
}
template <class Impl>
-Fault *
+Fault
SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
{
// Check if the instruction exists within the cache.
@@ -236,7 +236,7 @@ SimpleFetch<Impl>::fetchCacheLine(Addr fetch_PC)
unsigned flags = 0;
#endif // FULL_SYSTEM
- Fault * fault = NoFault;
+ Fault fault = NoFault;
// Align the fetch PC so it's at the start of a cache block.
fetch_PC = icacheBlockAlignPC(fetch_PC);
@@ -468,7 +468,7 @@ SimpleFetch<Impl>::fetch()
Addr fetch_PC = cpu->readPC();
// Fault code for memory access.
- Fault * fault = NoFault;
+ Fault fault = NoFault;
// If returning from the delay of a cache miss, then update the status
// to running, otherwise do the cache access. Possibly move this up
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 021f9b0b6..ee7b8858e 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -215,8 +215,8 @@ class PhysRegFile
}
#if FULL_SYSTEM
- uint64_t readIpr(int idx, Fault * &fault);
- Fault * setIpr(int idx, uint64_t val);
+ uint64_t readIpr(int idx, Fault &fault);
+ Fault setIpr(int idx, uint64_t val);
InternalProcReg *getIpr() { return ipr; }
int readIntrFlag() { return intrflag; }
void setIntrFlag(int val) { intrflag = val; }
@@ -279,7 +279,7 @@ PhysRegFile<Impl>::PhysRegFile(unsigned _numPhysicalIntRegs,
//the DynInst level.
template <class Impl>
uint64_t
-PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
+PhysRegFile<Impl>::readIpr(int idx, Fault &fault)
{
uint64_t retval = 0; // return value, default 0
@@ -387,7 +387,7 @@ PhysRegFile<Impl>::readIpr(int idx, Fault * &fault)
extern int break_ipl;
template <class Impl>
-Fault *
+Fault
PhysRegFile<Impl>::setIpr(int idx, uint64_t val)
{
uint64_t old;