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authorKevin Lim <ktlim@umich.edu>2006-04-22 19:10:39 -0400
committerKevin Lim <ktlim@umich.edu>2006-04-22 19:10:39 -0400
commit6b4396111ba26fd16c7cf0047c4cb3e13036c298 (patch)
treebb986809ce7f4638da620fb0590422d26b3990e5 /cpu/ozone/front_end_impl.hh
parentbfc507e44ecc08c4ded037cf589e968f2ba42705 (diff)
downloadgem5-6b4396111ba26fd16c7cf0047c4cb3e13036c298.tar.xz
Updates for OzoneCPU.
cpu/static_inst.hh: Updates for new CPU, also include a classification of quiesce instructions. --HG-- extra : convert_revision : a34cd56da88fe57d7de24674fbb375bbf13f887f
Diffstat (limited to 'cpu/ozone/front_end_impl.hh')
-rw-r--r--cpu/ozone/front_end_impl.hh13
1 files changed, 11 insertions, 2 deletions
diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh
index 0136d0ef0..af452fe95 100644
--- a/cpu/ozone/front_end_impl.hh
+++ b/cpu/ozone/front_end_impl.hh
@@ -48,6 +48,7 @@ FrontEnd<Impl>::FrontEnd(Params *params)
#if !FULL_SYSTEM
pTable = params->pTable;
#endif
+ fetchFault = NoFault;
}
template <class Impl>
@@ -273,6 +274,7 @@ FrontEnd<Impl>::tick()
Fault fault = fetchCacheLine();
if (fault != NoFault) {
handleFault(fault);
+ fetchFault = fault;
return;
}
fetchCacheLineNextCycle = false;
@@ -349,7 +351,7 @@ FrontEnd<Impl>::fetchCacheLine()
// Read a cache line, based on the current PC.
#if FULL_SYSTEM
// Flag to say whether or not address is physical addr.
- unsigned flags = cpu->inPalMode() ? PHYSICAL : 0;
+ unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0;
#else
unsigned flags = 0;
#endif // FULL_SYSTEM
@@ -503,6 +505,9 @@ FrontEnd<Impl>::squash(const InstSeqNum &squash_num, const Addr &next_PC,
DPRINTF(FE, "Squashing from [sn:%lli], setting PC to %#x\n",
squash_num, next_PC);
+ if (fetchFault != NoFault)
+ fetchFault = NoFault;
+
while (!instBuffer.empty() &&
instBuffer.back()->seqNum > squash_num) {
DynInstPtr inst = instBuffer.back();
@@ -604,9 +609,13 @@ FrontEnd<Impl>::addFreeRegs(int num_freed)
status = Running;
}
+ DPRINTF(FE, "Adding %i freed registers\n", num_freed);
+
freeRegs+= num_freed;
- assert(freeRegs <= numPhysRegs);
+// assert(freeRegs <= numPhysRegs);
+ if (freeRegs > numPhysRegs)
+ freeRegs = numPhysRegs;
}
template <class Impl>