Updates to bring CPU portion of m5 up-to-date with newmem.

--HG--
extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4

8 files changed, 168 insertions, 160 deletions

diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh
index 5af2b02b2..c272528b1 100644
--- a/cpu/ozone/cpu.hh
+++ b/cpu/ozone/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -79,13 +79,13 @@ template <class>
 class Checker;
 
 /**
- * Declaration of Out-of-Order CPU class.  Basically it is a SimpleCPU with
- * simple out-of-order capabilities added to it.  It is still a 1 CPI machine
- * (?), but is capable of handling cache misses.  Basically it models having
- * a ROB/IQ by only allowing a certain amount of instructions to execute while
- * the cache miss is outstanding.
+ * Light weight out of order CPU model that approximates an out of
+ * order CPU.  It is separated into a front end and a back end, with
+ * the template parameter Impl describing the classes used for each.
+ * The goal is to be able to specify through the Impl the class to use
+ * for the front end and back end, with different classes used to
+ * model different levels of detail.
  */
-
 template <class Impl>
 class OzoneCPU : public BaseCPU
 {
@@ -98,6 +98,11 @@ class OzoneCPU : public BaseCPU
     typedef TheISA::MiscReg MiscReg;
 
   public:
+    /**
+     * The ExecContext for this CPU, which is used to provide the
+     * CPU's interface to any external objects.  Internally most of
+     * the CPU state is stored within the OzoneThreadState class.
+     */
     class OzoneXC : public ExecContext {
       public:
         OzoneCPU<Impl> *cpu;
@@ -235,14 +240,19 @@ class OzoneCPU : public BaseCPU
 #endif
     };
 
-    // execution context proxy
+    // ExecContext for OzoneCPU
     OzoneXC ozoneXC;
+
+    // ExecContext pointer that will be given to any external objects.
     ExecContext *xcProxy;
+
+    // ExecContext pointer to the CheckerCPU's ExecContext.
     ExecContext *checkerXC;
 
     typedef OzoneThreadState<Impl> ImplState;
 
   private:
+    // Committed thread state for the OzoneCPU.
     OzoneThreadState<Impl> thread;
 
   public:
@@ -280,12 +290,6 @@ class OzoneCPU : public BaseCPU
             tickEvent.squash();
     }
 
-  private:
-    Trace::InstRecord *traceData;
-
-    template<typename T>
-    void trace_data(T data);
-
   public:
     enum Status {
         Running,
@@ -361,6 +365,7 @@ class OzoneCPU : public BaseCPU
     FrontEnd *frontEnd;
 
     BackEnd *backEnd;
+
   private:
     Status status() const { return _status; }
     void setStatus(Status new_status) { _status = new_status; }
@@ -392,12 +397,11 @@ class OzoneCPU : public BaseCPU
     // number of idle cycles
     Stats::Average<> notIdleFraction;
     Stats::Formula idleFraction;
-  public:
 
+  public:
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-
 #if FULL_SYSTEM
     bool validInstAddr(Addr addr) { return true; }
     bool validDataAddr(Addr addr) { return true; }
@@ -585,12 +589,9 @@ class OzoneCPU : public BaseCPU
 
     Fault copy(Addr dest);
 
-    InstSeqNum globalSeqNum;
-
   public:
     void squashFromXC();
 
-    // @todo: This can be a useful debug function.  Implement it.
     void dumpInsts() { frontEnd->dumpInsts(); }
 
 #if FULL_SYSTEM
@@ -608,7 +609,6 @@ class OzoneCPU : public BaseCPU
 
     ExecContext *xcBase() { return xcProxy; }
 
-    bool decoupledFrontEnd;
     struct CommStruct {
         InstSeqNum doneSeqNum;
         InstSeqNum nonSpecSeqNum;
@@ -617,8 +617,13 @@ class OzoneCPU : public BaseCPU
 
         bool stall;
     };
+
+    InstSeqNum globalSeqNum;
+
     TimeBuffer<CommStruct> comm;
 
+    bool decoupledFrontEnd;
+
     bool lockFlag;
 
     Stats::Scalar<> quiesceCycles;
diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh
index 5675da3a8..4f41f220a 100644
--- a/cpu/ozone/cpu_impl.hh
+++ b/cpu/ozone/cpu_impl.hh
@@ -26,9 +26,6 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-//#include <cstdio>
-//#include <cstdlib>
-
 #include "arch/isa_traits.hh" // For MachInst
 #include "base/trace.hh"
 #include "config/full_system.hh"
@@ -39,7 +36,6 @@
 #include "cpu/ozone/cpu.hh"
 #include "cpu/quiesce_event.hh"
 #include "cpu/static_inst.hh"
-//#include "mem/base_mem.hh"
 #include "mem/mem_interface.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
@@ -50,7 +46,6 @@
 #include "arch/alpha/tlb.hh"
 #include "arch/vtophys.hh"
 #include "base/callback.hh"
-//#include "base/remote_gdb.hh"
 #include "cpu/profile.hh"
 #include "kern/kernel_stats.hh"
 #include "mem/functional/memory_control.hh"
@@ -67,15 +62,6 @@
 using namespace TheISA;
 
 template <class Impl>
-template<typename T>
-void
-OzoneCPU<Impl>::trace_data(T data) {
-    if (traceData) {
-        traceData->setData(data);
-    }
-}
-
-template <class Impl>
 OzoneCPU<Impl>::TickEvent::TickEvent(OzoneCPU *c, int w)
     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
 {
@@ -104,7 +90,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width),
       mem(p->workload[0]->getMemory()),
 #endif
-      comm(5, 5)
+      comm(5, 5), decoupledFrontEnd(p->decoupledFrontEnd)
 {
     frontEnd = new FrontEnd(p);
     backEnd = new BackEnd(p);
@@ -112,6 +98,9 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     _status = Idle;
 
     if (p->checker) {
+        // If checker is being used, get the checker from the params
+        // pointer, make the Checker's ExecContext, and setup the
+        // xcProxy to point to it.
         BaseCPU *temp_checker = p->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
         checker->setMemory(mem);
@@ -122,11 +111,17 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
         thread.xcProxy = checkerXC;
         xcProxy = checkerXC;
     } else {
+        // If checker is not being used, then the xcProxy points
+        // directly to the CPU's ExecContext.
         checker = NULL;
         thread.xcProxy = &ozoneXC;
         xcProxy = &ozoneXC;
     }
 
+    // Add xcProxy to CPU list of ExecContexts.
+    execContexts.push_back(xcProxy);
+
+    // Give the OzoneXC pointers to the CPU and the thread state.
     ozoneXC.cpu = this;
     ozoneXC.thread = &thread;
 
@@ -134,7 +129,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 
     thread.setStatus(ExecContext::Suspended);
 #if FULL_SYSTEM
-    /***** All thread state stuff *****/
+    // Setup thread state stuff.
     thread.cpu = this;
     thread.tid = 0;
     thread.mem = p->mem;
@@ -171,8 +166,7 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     numInst = 0;
     startNumInst = 0;
 
-    execContexts.push_back(xcProxy);
-
+    // Give pointers to the front and back end to all things they may need.
     frontEnd->setCPU(this);
     backEnd->setCPU(this);
 
@@ -188,12 +182,13 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
     frontEnd->setBackEnd(backEnd);
     backEnd->setFrontEnd(frontEnd);
 
-    decoupledFrontEnd = p->decoupledFrontEnd;
-
     globalSeqNum = 1;
 
     checkInterrupts = false;
 
+    lockFlag = 0;
+
+    // Setup rename table, initializing all values to ready.
     for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
         thread.renameTable[i] = new DynInst(this);
         thread.renameTable[i]->setResultReady();
@@ -206,8 +201,6 @@ OzoneCPU<Impl>::OzoneCPU(Params *p)
 //    pTable = p->pTable;
 #endif
 
-    lockFlag = 0;
-
     DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n");
 }
 
@@ -231,14 +224,20 @@ template <class Impl>
 void
 OzoneCPU<Impl>::signalSwitched()
 {
+    // Only complete the switchout when both the front end and back
+    // end have signalled they are ready to switch.
     if (++switchCount == 2) {
         backEnd->doSwitchOut();
         frontEnd->doSwitchOut();
+
         if (checker)
             checker->switchOut(sampler);
+
         _status = SwitchedOut;
+
         if (tickEvent.scheduled())
             tickEvent.squash();
+
         sampler->signalSwitched();
     }
     assert(switchCount <= 2);
@@ -793,6 +792,7 @@ OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
         thread->quiesceEvent->xc = this;
     }
 
+    // Copy kernel stats pointer from old context.
     thread->kernelStats = old_context->getKernelStats();
 //    storeCondFailures = 0;
     cpu->lockFlag = false;
@@ -814,7 +814,11 @@ OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
 template <class Impl>
 void
 OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os)
-{ }
+{
+    // Once serialization is added, serialize the quiesce event and
+    // kernel stats.  Will need to make sure there aren't multiple
+    // things that serialize them.
+}
 
 template <class Impl>
 void
@@ -867,7 +871,6 @@ OzoneCPU<Impl>::OzoneXC::getThreadNum()
     return thread->tid;
 }
 
-// Also somewhat obnoxious.  Really only used for the TLB fault.
 template <class Impl>
 TheISA::MachInst
 OzoneCPU<Impl>::OzoneXC::getInst()
@@ -901,7 +904,7 @@ OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc)
 
     // Need to copy the XC values into the current rename table,
     // copy the misc regs.
-    thread->regs.miscRegs.copyMiscRegs(xc);
+    TheISA::copyMiscRegs(xc, this);
 }
 
 template <class Impl>
diff --git a/cpu/ozone/inorder_back_end_impl.hh b/cpu/ozone/inorder_back_end_impl.hh
index 5a378ec76..cc92ec92f 100644
--- a/cpu/ozone/inorder_back_end_impl.hh
+++ b/cpu/ozone/inorder_back_end_impl.hh
@@ -257,7 +257,7 @@ InorderBackEnd<Impl>::executeInsts()
         }
 
         inst->setExecuted();
-        inst->setCompleted();
+        inst->setResultReady();
         inst->setCanCommit();
 
         instList.pop_front();
diff --git a/cpu/ozone/inst_queue_impl.hh b/cpu/ozone/inst_queue_impl.hh
index 0523c68d6..1b9fcdc84 100644
--- a/cpu/ozone/inst_queue_impl.hh
+++ b/cpu/ozone/inst_queue_impl.hh
@@ -848,13 +848,13 @@ template <class Impl>
 void
 InstQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
 {
-    OpClass op_class = ready_inst->opClass();
+//    OpClass op_class = ready_inst->opClass();
 
     readyInsts.push(ready_inst);
 
     DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
             "the ready list, PC %#x opclass:%i [sn:%lli].\n",
-            ready_inst->readPC(), op_class, ready_inst->seqNum);
+            ready_inst->readPC(), ready_inst->opClass(), ready_inst->seqNum);
 }
 /*
 template <class Impl>
@@ -1175,11 +1175,11 @@ InstQueue<Impl>::addIfReady(DynInstPtr &inst)
             return;
         }
 
-        OpClass op_class = inst->opClass();
+//        OpClass op_class = inst->opClass();
 
         DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
                 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
-                inst->readPC(), op_class, inst->seqNum);
+                inst->readPC(), inst->opClass(), inst->seqNum);
 
         readyInsts.push(inst);
     }
diff --git a/cpu/ozone/lw_back_end.hh b/cpu/ozone/lw_back_end.hh
index 1c03ffb73..19f2b2b61 100644
--- a/cpu/ozone/lw_back_end.hh
+++ b/cpu/ozone/lw_back_end.hh
@@ -369,37 +369,37 @@ class LWBackEnd
 /*    Stats::Scalar<> dcacheStallCycles;
       Counter lastDcacheStall;
 */
-    Stats::Vector<> rob_cap_events;
-    Stats::Vector<> rob_cap_inst_count;
-    Stats::Vector<> iq_cap_events;
-    Stats::Vector<> iq_cap_inst_count;
+    Stats::Vector<> robCapEvents;
+    Stats::Vector<> robCapInstCount;
+    Stats::Vector<> iqCapEvents;
+    Stats::Vector<> iqCapInstCount;
     // total number of instructions executed
-    Stats::Vector<> exe_inst;
-    Stats::Vector<> exe_swp;
-    Stats::Vector<> exe_nop;
-    Stats::Vector<> exe_refs;
-    Stats::Vector<> exe_loads;
-    Stats::Vector<> exe_branches;
+    Stats::Vector<> exeInst;
+    Stats::Vector<> exeSwp;
+    Stats::Vector<> exeNop;
+    Stats::Vector<> exeRefs;
+    Stats::Vector<> exeLoads;
+    Stats::Vector<> exeBranches;
 
-    Stats::Vector<> issued_ops;
+    Stats::Vector<> issuedOps;
 
     // total number of loads forwaded from LSQ stores
-    Stats::Vector<> lsq_forw_loads;
+    Stats::Vector<> lsqForwLoads;
 
     // total number of loads ignored due to invalid addresses
-    Stats::Vector<> inv_addr_loads;
+    Stats::Vector<> invAddrLoads;
 
     // total number of software prefetches ignored due to invalid addresses
-    Stats::Vector<> inv_addr_swpfs;
+    Stats::Vector<> invAddrSwpfs;
     // ready loads blocked due to memory disambiguation
-    Stats::Vector<> lsq_blocked_loads;
+    Stats::Vector<> lsqBlockedLoads;
 
     Stats::Scalar<> lsqInversion;
 
-    Stats::Vector<> n_issued_dist;
-    Stats::VectorDistribution<> issue_delay_dist;
+    Stats::Vector<> nIssuedDist;
+    Stats::VectorDistribution<> issueDelayDist;
 
-    Stats::VectorDistribution<> queue_res_dist;
+    Stats::VectorDistribution<> queueResDist;
 /*
     Stats::Vector<> stat_fu_busy;
     Stats::Vector2d<> stat_fuBusy;
@@ -417,37 +417,37 @@ class LWBackEnd
     Stats::Formula commit_ipb;
     Stats::Formula lsq_inv_rate;
 */
-    Stats::Vector<> writeback_count;
-    Stats::Vector<> producer_inst;
-    Stats::Vector<> consumer_inst;
-    Stats::Vector<> wb_penalized;
+    Stats::Vector<> writebackCount;
+    Stats::Vector<> producerInst;
+    Stats::Vector<> consumerInst;
+    Stats::Vector<> wbPenalized;
 
-    Stats::Formula wb_rate;
-    Stats::Formula wb_fanout;
-    Stats::Formula wb_penalized_rate;
+    Stats::Formula wbRate;
+    Stats::Formula wbFanout;
+    Stats::Formula wbPenalizedRate;
 
     // total number of instructions committed
-    Stats::Vector<> stat_com_inst;
-    Stats::Vector<> stat_com_swp;
-    Stats::Vector<> stat_com_refs;
-    Stats::Vector<> stat_com_loads;
-    Stats::Vector<> stat_com_membars;
-    Stats::Vector<> stat_com_branches;
+    Stats::Vector<> statComInst;
+    Stats::Vector<> statComSwp;
+    Stats::Vector<> statComRefs;
+    Stats::Vector<> statComLoads;
+    Stats::Vector<> statComMembars;
+    Stats::Vector<> statComBranches;
 
-    Stats::Distribution<> n_committed_dist;
+    Stats::Distribution<> nCommittedDist;
 
-    Stats::Scalar<> commit_eligible_samples;
-    Stats::Vector<> commit_eligible;
+    Stats::Scalar<> commitEligibleSamples;
+    Stats::Vector<> commitEligible;
 
     Stats::Vector<> squashedInsts;
     Stats::Vector<> ROBSquashedInsts;
 
-    Stats::Scalar<> ROB_fcount;
-    Stats::Formula ROB_full_rate;
+    Stats::Scalar<> ROBFcount;
+    Stats::Formula ROBFullRate;
 
-    Stats::Vector<>  ROB_count;	 // cumulative ROB occupancy
-    Stats::Formula ROB_occ_rate;
-    Stats::VectorDistribution<> ROB_occ_dist;
+    Stats::Vector<>  ROBCount;	 // cumulative ROB occupancy
+    Stats::Formula ROBOccRate;
+    Stats::VectorDistribution<> ROBOccDist;
   public:
     void dumpInsts();
 
diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh
index 41b4ea24b..18b2e8f47 100644
--- a/cpu/ozone/lw_back_end_impl.hh
+++ b/cpu/ozone/lw_back_end_impl.hh
@@ -251,78 +251,77 @@ void
 LWBackEnd<Impl>::regStats()
 {
     using namespace Stats;
-    rob_cap_events
+    robCapEvents
         .init(cpu->number_of_threads)
         .name(name() + ".ROB:cap_events")
         .desc("number of cycles where ROB cap was active")
         .flags(total)
         ;
 
-    rob_cap_inst_count
+    robCapInstCount
         .init(cpu->number_of_threads)
         .name(name() + ".ROB:cap_inst")
         .desc("number of instructions held up by ROB cap")
         .flags(total)
         ;
 
-    iq_cap_events
+    iqCapEvents
         .init(cpu->number_of_threads)
         .name(name() +".IQ:cap_events" )
         .desc("number of cycles where IQ cap was active")
         .flags(total)
         ;
 
-    iq_cap_inst_count
+    iqCapInstCount
         .init(cpu->number_of_threads)
         .name(name() + ".IQ:cap_inst")
         .desc("number of instructions held up by IQ cap")
         .flags(total)
         ;
 
-
-    exe_inst
+    exeInst
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:count")
         .desc("number of insts issued")
         .flags(total)
         ;
 
-    exe_swp
+    exeSwp
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:swp")
         .desc("number of swp insts issued")
         .flags(total)
         ;
 
-    exe_nop
+    exeNop
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:nop")
         .desc("number of nop insts issued")
         .flags(total)
         ;
 
-    exe_refs
+    exeRefs
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:refs")
         .desc("number of memory reference insts issued")
         .flags(total)
         ;
 
-    exe_loads
+    exeLoads
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:loads")
         .desc("number of load insts issued")
         .flags(total)
         ;
 
-    exe_branches
+    exeBranches
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:branches")
         .desc("Number of branches issued")
         .flags(total)
         ;
 
-    issued_ops
+    issuedOps
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:op_count")
         .desc("number of insts issued")
@@ -339,28 +338,28 @@ LWBackEnd<Impl>::regStats()
     //
     //  Other stats
     //
-    lsq_forw_loads
+    lsqForwLoads
         .init(cpu->number_of_threads)
         .name(name() + ".LSQ:forw_loads")
         .desc("number of loads forwarded via LSQ")
         .flags(total)
         ;
 
-    inv_addr_loads
+    invAddrLoads
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:addr_loads")
         .desc("number of invalid-address loads")
         .flags(total)
         ;
 
-    inv_addr_swpfs
+    invAddrSwpfs
         .init(cpu->number_of_threads)
         .name(name() + ".ISSUE:addr_swpfs")
         .desc("number of invalid-address SW prefetches")
         .flags(total)
         ;
 
-    lsq_blocked_loads
+    lsqBlockedLoads
         .init(cpu->number_of_threads)
         .name(name() + ".LSQ:blocked_loads")
         .desc("number of ready loads not issued due to memory disambiguation")
@@ -372,51 +371,51 @@ LWBackEnd<Impl>::regStats()
         .desc("Number of times LSQ instruction issued early")
         ;
 
-    n_issued_dist
+    nIssuedDist
         .init(issueWidth + 1)
         .name(name() + ".ISSUE:issued_per_cycle")
         .desc("Number of insts issued each cycle")
         .flags(total | pdf | dist)
         ;
-    issue_delay_dist
+    issueDelayDist
         .init(Num_OpClasses,0,99,2)
         .name(name() + ".ISSUE:")
         .desc("cycles from operands ready to issue")
         .flags(pdf | cdf)
         ;
 
-    queue_res_dist
+    queueResDist
         .init(Num_OpClasses, 0, 99, 2)
         .name(name() + ".IQ:residence:")
         .desc("cycles from dispatch to issue")
         .flags(total | pdf | cdf )
         ;
     for (int i = 0; i < Num_OpClasses; ++i) {
-        queue_res_dist.subname(i, opClassStrings[i]);
+        queueResDist.subname(i, opClassStrings[i]);
     }
 
-    writeback_count
+    writebackCount
         .init(cpu->number_of_threads)
         .name(name() + ".WB:count")
         .desc("cumulative count of insts written-back")
         .flags(total)
         ;
 
-    producer_inst
+    producerInst
         .init(cpu->number_of_threads)
         .name(name() + ".WB:producers")
         .desc("num instructions producing a value")
         .flags(total)
         ;
 
-    consumer_inst
+    consumerInst
         .init(cpu->number_of_threads)
         .name(name() + ".WB:consumers")
         .desc("num instructions consuming a value")
         .flags(total)
         ;
 
-    wb_penalized
+    wbPenalized
         .init(cpu->number_of_threads)
         .name(name() + ".WB:penalized")
         .desc("number of instrctions required to write to 'other' IQ")
@@ -424,71 +423,71 @@ LWBackEnd<Impl>::regStats()
         ;
 
 
-    wb_penalized_rate
+    wbPenalizedRate
         .name(name() + ".WB:penalized_rate")
         .desc ("fraction of instructions written-back that wrote to 'other' IQ")
         .flags(total)
         ;
 
-    wb_penalized_rate = wb_penalized / writeback_count;
+    wbPenalizedRate = wbPenalized / writebackCount;
 
-    wb_fanout
+    wbFanout
         .name(name() + ".WB:fanout")
         .desc("average fanout of values written-back")
         .flags(total)
         ;
 
-    wb_fanout = producer_inst / consumer_inst;
+    wbFanout = producerInst / consumerInst;
 
-    wb_rate
+    wbRate
         .name(name() + ".WB:rate")
         .desc("insts written-back per cycle")
         .flags(total)
         ;
-    wb_rate = writeback_count / cpu->numCycles;
+    wbRate = writebackCount / cpu->numCycles;
 
-    stat_com_inst
+    statComInst
         .init(cpu->number_of_threads)
         .name(name() + ".COM:count")
         .desc("Number of instructions committed")
         .flags(total)
         ;
 
-    stat_com_swp
+    statComSwp
         .init(cpu->number_of_threads)
         .name(name() + ".COM:swp_count")
         .desc("Number of s/w prefetches committed")
         .flags(total)
         ;
 
-    stat_com_refs
+    statComRefs
         .init(cpu->number_of_threads)
         .name(name() +  ".COM:refs")
         .desc("Number of memory references committed")
         .flags(total)
         ;
 
-    stat_com_loads
+    statComLoads
         .init(cpu->number_of_threads)
         .name(name() +  ".COM:loads")
         .desc("Number of loads committed")
         .flags(total)
         ;
 
-    stat_com_membars
+    statComMembars
         .init(cpu->number_of_threads)
         .name(name() +  ".COM:membars")
         .desc("Number of memory barriers committed")
         .flags(total)
         ;
 
-    stat_com_branches
+    statComBranches
         .init(cpu->number_of_threads)
         .name(name() + ".COM:branches")
         .desc("Number of branches committed")
         .flags(total)
         ;
-    n_committed_dist
+    nCommittedDist
         .init(0,commitWidth,1)
         .name(name() + ".COM:committed_per_cycle")
         .desc("Number of insts commited each cycle")
@@ -508,14 +507,14 @@ LWBackEnd<Impl>::regStats()
     //  -> The standard deviation is computed only over cycles where
     //  we reached the BW limit
     //
-    commit_eligible
+    commitEligible
         .init(cpu->number_of_threads)
         .name(name() + ".COM:bw_limited")
         .desc("number of insts not committed due to BW limits")
         .flags(total)
         ;
 
-    commit_eligible_samples
+    commitEligibleSamples
         .name(name() + ".COM:bw_lim_events")
         .desc("number cycles where commit BW limit reached")
         ;
@@ -532,32 +531,32 @@ LWBackEnd<Impl>::regStats()
         .desc("Number of instructions removed from inst list when they reached the head of the ROB")
         ;
 
-    ROB_fcount
+    ROBFcount
         .name(name() + ".ROB:full_count")
         .desc("number of cycles where ROB was full")
         ;
 
-    ROB_count
+    ROBCount
         .init(cpu->number_of_threads)
         .name(name() + ".ROB:occupancy")
         .desc(name() + ".ROB occupancy (cumulative)")
         .flags(total)
         ;
 
-    ROB_full_rate
+    ROBFullRate
         .name(name() + ".ROB:full_rate")
         .desc("ROB full per cycle")
         ;
-    ROB_full_rate = ROB_fcount / cpu->numCycles;
+    ROBFullRate = ROBFcount / cpu->numCycles;
 
-    ROB_occ_rate
+    ROBOccRate
         .name(name() + ".ROB:occ_rate")
         .desc("ROB occupancy rate")
         .flags(total)
         ;
-    ROB_occ_rate = ROB_count / cpu->numCycles;
+    ROBOccRate = ROBCount / cpu->numCycles;
 
-    ROB_occ_dist
+    ROBOccDist
         .init(cpu->number_of_threads,0,numROBEntries,2)
         .name(name() + ".ROB:occ_dist")
         .desc("ROB Occupancy per cycle")
@@ -660,7 +659,7 @@ LWBackEnd<Impl>::tick()
         return;
     }
 
-    ROB_count[0]+= numInsts;
+    ROBCount[0]+= numInsts;
 
     wbCycle = 0;
 
@@ -980,8 +979,8 @@ LWBackEnd<Impl>::executeInsts()
         }
     }
 
-    issued_ops[0]+= num_executed;
-    n_issued_dist[num_executed]++;
+    issuedOps[0]+= num_executed;
+    nIssuedDist[num_executed]++;
 }
 
 template<class Impl>
@@ -1002,13 +1001,13 @@ LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
             inst->setResultReady();
             int dependents = wakeDependents(inst);
             if (dependents) {
-                producer_inst[0]++;
-                consumer_inst[0]+= dependents;
+                producerInst[0]++;
+                consumerInst[0]+= dependents;
             }
         }
     }
 
-    writeback_count[0]++;
+    writebackCount[0]++;
 }
 #if 0
 template <class Impl>
@@ -1076,7 +1075,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
 
     thread->setPC(inst->readPC());
     thread->setNextPC(inst->readNextPC());
-    inst->reachedCommit = true;
+    inst->setAtCommit();
 
     // If the instruction is not executed yet, then it is a non-speculative
     // or store inst.  Signal backwards that it should be executed.
@@ -1229,6 +1228,9 @@ LWBackEnd<Impl>::commitInst(int inst_num)
         inst->traceData = NULL;
     }
 
+    if (inst->isCopy())
+        panic("Should not commit any copy instructions!");
+
     inst->clearDependents();
 
     frontEnd->addFreeRegs(freed_regs);
@@ -1292,7 +1294,7 @@ LWBackEnd<Impl>::commitInsts()
             break;
         }
     }
-    n_committed_dist.sample(inst_num);
+    nCommittedDist.sample(inst_num);
 }
 
 template <class Impl>
@@ -1344,7 +1346,7 @@ LWBackEnd<Impl>::squash(const InstSeqNum &sn)
 
         (*insts_it)->setCanCommit();
 
-        (*insts_it)->removeInROB();
+        (*insts_it)->clearInROB();
 
         for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
             DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
@@ -1522,27 +1524,27 @@ LWBackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
     //
 #ifdef TARGET_ALPHA
     if (inst->isDataPrefetch())
-        exe_swp[thread_number]++;
+        exeSwp[thread_number]++;
     else
-        exe_inst[thread_number]++;
+        exeInst[thread_number]++;
 #else
-    exe_inst[thread_number]++;
+    exeInst[thread_number]++;
 #endif
 
     //
     //  Control operations
     //
     if (inst->isControl())
-        exe_branches[thread_number]++;
+        exeBranches[thread_number]++;
 
     //
     //  Memory operations
     //
     if (inst->isMemRef()) {
-        exe_refs[thread_number]++;
+        exeRefs[thread_number]++;
 
         if (inst->isLoad())
-            exe_loads[thread_number]++;
+            exeLoads[thread_number]++;
     }
 }
 
@@ -1562,33 +1564,33 @@ LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
     //
 #ifdef TARGET_ALPHA
     if (inst->isDataPrefetch()) {
-        stat_com_swp[tid]++;
+        statComSwp[tid]++;
     } else {
-        stat_com_inst[tid]++;
+        statComInst[tid]++;
     }
 #else
-    stat_com_inst[tid]++;
+    statComInst[tid]++;
 #endif
 
     //
     //  Control Instructions
     //
     if (inst->isControl())
-        stat_com_branches[tid]++;
+        statComBranches[tid]++;
 
     //
     //  Memory references
     //
     if (inst->isMemRef()) {
-        stat_com_refs[tid]++;
+        statComRefs[tid]++;
 
         if (inst->isLoad()) {
-            stat_com_loads[tid]++;
+            statComLoads[tid]++;
         }
     }
 
     if (inst->isMemBarrier()) {
-        stat_com_membars[tid]++;
+        statComMembars[tid]++;
     }
 }
 
diff --git a/cpu/ozone/lw_lsq.hh b/cpu/ozone/lw_lsq.hh
index 6fe343b42..c0bf0b0fe 100644
--- a/cpu/ozone/lw_lsq.hh
+++ b/cpu/ozone/lw_lsq.hh
@@ -447,7 +447,7 @@ OzoneLWLSQ<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     // too).
     // @todo: Fix uncached accesses.
     if (req->flags & UNCACHEABLE &&
-        (inst != loadQueue.back() || !inst->reachedCommit)) {
+        (inst != loadQueue.back() || !inst->isAtCommit())) {
         DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of "
                 "commit/LSQ!\n",
                 inst->seqNum);
diff --git a/cpu/ozone/thread_state.hh b/cpu/ozone/thread_state.hh
index c86c3a720..f104dff23 100644
--- a/cpu/ozone/thread_state.hh
+++ b/cpu/ozone/thread_state.hh
@@ -182,8 +182,6 @@ struct OzoneThreadState : public ThreadState {
     void setNextPC(uint64_t val)
     { nextPC = val; }
 
-    bool misspeculating() { return false; }
-
     void setInst(TheISA::MachInst _inst) { inst = _inst; }
 
     Counter readFuncExeInst() { return funcExeInst; }