diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-31 20:32:18 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-31 20:32:18 -0500 |
| commit | adeb458b878d0768fd4de82bc1997512dc65e6d3 (patch) | |
| tree | d7b27950803618125f7c2fcfa3353e4e40e0166c /cpu/simple/cpu.cc | |
| parent | 5c79eb04104e6e3dd2fd957c071fef3ceb47b722 (diff) | |
| parent | 5936c79ba0f3fd29ef2bbf41fcaddc78fcd9c75c (diff) | |
| download | gem5-adeb458b878d0768fd4de82bc1997512dc65e6d3.tar.xz | |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 08ae5e999d9b313e3e40cb6d58863905b70ca781
Diffstat (limited to 'cpu/simple/cpu.cc')
| -rw-r--r-- | cpu/simple/cpu.cc | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 4aaf81fa0..88c99c566 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -64,8 +64,8 @@ #if FULL_SYSTEM #include "base/remote_gdb.hh" -#include "mem/functional/memory_control.hh" -#include "mem/functional/physical.hh" +//#include "mem/functional/memory_control.hh" +//#include "mem/functional/physical.hh" #include "sim/system.hh" #include "arch/tlb.hh" #include "arch/stacktrace.hh" @@ -155,16 +155,21 @@ SimpleCPU::CpuPort::recvRetry() } SimpleCPU::SimpleCPU(Params *p) +#if !FULL_SYSTEM : BaseCPU(p), mem(p->mem), icachePort(this), dcachePort(this), tickEvent(this, p->width), cpuXC(NULL) +#else + : BaseCPU(p), icachePort(this), dcachePort(this), + tickEvent(this, p->width), cpuXC(NULL) +#endif { _status = Idle; #if FULL_SYSTEM - cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); + cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb); #else - cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0, - &dcachePort); + cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process, + /* asid */ 0, mem); #endif // !FULL_SYSTEM xcProxy = cpuXC->getProxy(); @@ -899,7 +904,7 @@ SimpleCPU::tick() #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && - status() != IcacheMissComplete) { + status() != IcacheAccessComplete) { int ipl = 0; int summary = 0; checkInterrupts = false; |