More changes toward making simpleCpu use new port interface.

cpu/simple/cpu.cc:
    Initialize the ports, also add Request and Packet instead of MemReq.  Initial work at ICache read in place.
cpu/simple/cpu.hh:
    Need to call the completion handler when we see a recieve.

--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359

1 files changed, 5 insertions, 11 deletions

diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 0fb6235b4..ac4e1cf22 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -80,13 +80,13 @@ class SimpleCPU : public BaseCPU
       protected:
 
         virtual bool recvTiming(Packet &pkt)
-        { return cpu->recvTiming(pkt); }
+        { return cpu->processCacheCompletion(pkt); }
 
         virtual Tick recvAtomic(Packet &pkt)
-        { return cpu->recvAtomic(pkt); }
+        { return cpu->processCacheCompletion(pkt); }
 
         virtual void recvFunctional(Packet &pkt)
-        { cpu->recvFunctional(pkt); }
+        { cpu->processCacheCompletion(pkt); }
 
         virtual void recvStatusChange(Status status)
         { cpu->recvStatusChange(status); }
@@ -192,17 +192,11 @@ class SimpleCPU : public BaseCPU
     bool interval_stats;
 #endif
 
-    // L1 instruction cache
-    MemInterface *icacheInterface;
-
-    // L1 data cache
-    MemInterface *dcacheInterface;
-
     // current instruction
     MachInst inst;
 
-    // Refcounted pointer to the one memory request.
-    MemReqPtr memReq;
+    CpuRequest *req;
+    Packet *pkt;
 
     // Pointer to the sampler that is telling us to switchover.
     // Used to signal the completion of the pipe drain and schedule