Split SimpleCPU into two different models, AtomicSimpleCPU and

TimingSimpleCPU, which use atomic and timing memory accesses
respectively.  Common code is factored into the BaseSimpleCPU class.
AtomicSimpleCPU includes an option (simulate_stalls) to add delays
based on the estimated latency reported by the atomic accesses.
Plain old "SimpleCPU" is gone; I have not updated all the config
files (just test/test.py).
Also fixes to get timing accesses working in new memory model and
to get split-phase memory instruction definitions working with
new memory model as well.

arch/alpha/isa/main.isa:
    Need to include packet_impl.h for functions that use Packet objects.
arch/alpha/isa/mem.isa:
    Change completeAcc() methods to take Packet object pointers.
    Also split out StoreCond template for completeAcc(), since
    that's the only one that needs write_result and we get an
    unused variable warning if we always have it in there.
build/SConstruct:
    Update list of recognized CPU model names.
configs/test/test.py:
    Change SimpleCPU to AtomicSimpleCPU.
cpu/SConscript:
    Define sources for new CPU models.
    Add split memory access methods to CPU model signatures.
cpu/cpu_models.py:
cpu/static_inst.hh:
    Define new CPU models.
cpu/simple/base.cc:
cpu/simple/base.hh:
    Factor out pieces specific to Atomic or Timing models.
mem/bus.cc:
    Bus needs to be able to route timing packets based on explicit dest
    so responses can get back to requester.  Set dest to Packet::Broadcast
    to indicate that dest should be derived from address.
    Also set packet src field based on port from which packet is sent.
mem/bus.hh:
    Set packet src field based on port from which packet is sent.
mem/packet.hh:
    Define Broadcast destination address to indicate that
    packet should be routed based on address.
mem/physical.cc:
    Set packet dest on response so packet is routed
    back to requester properly.
mem/port.cc:
    Flag blob packets as Broadcast.
python/m5/objects/PhysicalMemory.py:
    Change default latency to be 1 cycle.

--HG--
rename : cpu/simple/cpu.cc => cpu/simple/base.cc
rename : cpu/simple/cpu.hh => cpu/simple/base.hh
extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132

1 files changed, 0 insertions, 431 deletions

diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
deleted file mode 100644
index 945de20af..000000000
--- a/cpu/simple/cpu.hh
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
-#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
-
-#include "base/statistics.hh"
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/cpu_exec_context.hh"
-#include "cpu/pc_event.hh"
-#include "cpu/sampler/sampler.hh"
-#include "cpu/static_inst.hh"
-#include "mem/packet.hh"
-#include "mem/port.hh"
-#include "mem/request.hh"
-#include "sim/eventq.hh"
-
-// forward declarations
-#if FULL_SYSTEM
-class Processor;
-class AlphaITB;
-class AlphaDTB;
-class MemObject;
-
-class RemoteGDB;
-class GDBListener;
-
-#else
-
-class Process;
-
-#endif // FULL_SYSTEM
-
-class ExecContext;
-class Checkpoint;
-
-namespace Trace {
-    class InstRecord;
-}
-
-
-// Set exactly one of these symbols to 1 to set the memory access
-// model.  Probably should make these template parameters, or even
-// just fork the CPU models.
-//
-#define SIMPLE_CPU_MEM_TIMING    0
-#define SIMPLE_CPU_MEM_ATOMIC    0
-#define SIMPLE_CPU_MEM_IMMEDIATE 1
-
-
-class SimpleCPU : public BaseCPU
-{
-  protected:
-    typedef TheISA::MachInst MachInst;
-    typedef TheISA::MiscReg MiscReg;
-    typedef TheISA::FloatReg FloatReg;
-    typedef TheISA::FloatRegBits FloatRegBits;
-    class CpuPort : public Port
-    {
-
-        SimpleCPU *cpu;
-
-      public:
-
-        CpuPort(SimpleCPU *_cpu)
-            : cpu(_cpu)
-        { }
-
-      protected:
-
-        virtual bool recvTiming(Packet &pkt);
-
-        virtual Tick recvAtomic(Packet &pkt);
-
-        virtual void recvFunctional(Packet &pkt);
-
-        virtual void recvStatusChange(Status status);
-
-        virtual Packet *recvRetry();
-
-        virtual void getDeviceAddressRanges(AddrRangeList &resp,
-            AddrRangeList &snoop)
-        { resp.clear(); snoop.clear(); }
-    };
-
-    MemObject *mem;
-    CpuPort icachePort;
-    CpuPort dcachePort;
-
-  public:
-    // main simulation loop (one cycle)
-    void tick();
-    virtual void init();
-
-  private:
-    struct TickEvent : public Event
-    {
-        SimpleCPU *cpu;
-        int width;
-
-        TickEvent(SimpleCPU *c, int w);
-        void process();
-        const char *description();
-    };
-
-    TickEvent tickEvent;
-
-    /// Schedule tick event, regardless of its current state.
-    void scheduleTickEvent(int numCycles)
-    {
-        if (tickEvent.squashed())
-            tickEvent.reschedule(curTick + cycles(numCycles));
-        else if (!tickEvent.scheduled())
-            tickEvent.schedule(curTick + cycles(numCycles));
-    }
-
-    /// Unschedule tick event, regardless of its current state.
-    void unscheduleTickEvent()
-    {
-        if (tickEvent.scheduled())
-            tickEvent.squash();
-    }
-
-  private:
-    Trace::InstRecord *traceData;
-
-  public:
-    //
-    enum Status {
-        Running,
-        Idle,
-        IcacheRetry,
-        IcacheWaitResponse,
-        IcacheAccessComplete,
-        DcacheRetry,
-        DcacheWaitResponse,
-        DcacheWaitSwitch,
-        SwitchedOut
-    };
-
-  private:
-    Status _status;
-
-  public:
-    void post_interrupt(int int_num, int index);
-
-    void zero_fill_64(Addr addr) {
-      static int warned = 0;
-      if (!warned) {
-        warn ("WH64 is not implemented");
-        warned = 1;
-      }
-    };
-
-  public:
-    struct Params : public BaseCPU::Params
-    {
-        int width;
-        MemObject *mem;
-#if FULL_SYSTEM
-        AlphaITB *itb;
-        AlphaDTB *dtb;
-#else
-        Process *process;
-#endif
-    };
-    SimpleCPU(Params *params);
-    virtual ~SimpleCPU();
-
-  public:
-    // execution context
-    CPUExecContext *cpuXC;
-
-    ExecContext *xcProxy;
-
-    void switchOut(Sampler *s);
-    void takeOverFrom(BaseCPU *oldCPU);
-
-#if FULL_SYSTEM
-    Addr dbg_vtophys(Addr addr);
-
-    bool interval_stats;
-#endif
-
-    // current instruction
-    MachInst inst;
-
-    // Static data storage
-    TheISA::IntReg dataReg;
-
-#if SIMPLE_CPU_MEM_TIMING
-    Packet *retry_pkt;
-#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
-    Request *ifetch_req;
-    Packet  *ifetch_pkt;
-    Request *data_read_req;
-    Packet  *data_read_pkt;
-    Request *data_write_req;
-    Packet  *data_write_pkt;
-#endif
-
-    // Pointer to the sampler that is telling us to switchover.
-    // Used to signal the completion of the pipe drain and schedule
-    // the next switchover
-    Sampler *sampler;
-
-    StaticInstPtr curStaticInst;
-
-    Status status() const { return _status; }
-
-    virtual void activateContext(int thread_num, int delay);
-    virtual void suspendContext(int thread_num);
-    virtual void deallocateContext(int thread_num);
-    virtual void haltContext(int thread_num);
-
-    // statistics
-    virtual void regStats();
-    virtual void resetStats();
-
-    // number of simulated instructions
-    Counter numInst;
-    Counter startNumInst;
-    Stats::Scalar<> numInsts;
-
-    virtual Counter totalInstructions() const
-    {
-        return numInst - startNumInst;
-    }
-
-    // number of simulated memory references
-    Stats::Scalar<> numMemRefs;
-
-    // number of simulated loads
-    Counter numLoad;
-    Counter startNumLoad;
-
-    // number of idle cycles
-    Stats::Average<> notIdleFraction;
-    Stats::Formula idleFraction;
-
-    // number of cycles stalled for I-cache responses
-    Stats::Scalar<> icacheStallCycles;
-    Counter lastIcacheStall;
-
-    // number of cycles stalled for I-cache retries
-    Stats::Scalar<> icacheRetryCycles;
-    Counter lastIcacheRetry;
-
-    // number of cycles stalled for D-cache responses
-    Stats::Scalar<> dcacheStallCycles;
-    Counter lastDcacheStall;
-
-    // number of cycles stalled for D-cache retries
-    Stats::Scalar<> dcacheRetryCycles;
-    Counter lastDcacheRetry;
-
-    void sendIcacheRequest(Packet *pkt);
-    void sendDcacheRequest(Packet *pkt);
-    void processResponse(Packet &response);
-
-    Packet * processRetry();
-    void recvStatusChange(Port::Status status) {}
-
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    template <class T>
-    Fault read(Addr addr, T &data, unsigned flags);
-
-    template <class T>
-    Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
-    // These functions are only used in CPU models that split
-    // effective address computation from the actual memory access.
-    void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
-    Addr getEA() 	{ panic("SimpleCPU::getEA() not implemented\n"); }
-
-    void prefetch(Addr addr, unsigned flags)
-    {
-        // need to do this...
-    }
-
-    void writeHint(Addr addr, int size, unsigned flags)
-    {
-        // need to do this...
-    }
-
-    Fault copySrcTranslate(Addr src);
-
-    Fault copy(Addr dest);
-
-    // The register accessor methods provide the index of the
-    // instruction's operand (e.g., 0 or 1), not the architectural
-    // register index, to simplify the implementation of register
-    // renaming.  We find the architectural register index by indexing
-    // into the instruction's own operand index table.  Note that a
-    // raw pointer to the StaticInst is provided instead of a
-    // ref-counted StaticInstPtr to redice overhead.  This is fine as
-    // long as these methods don't copy the pointer into any long-term
-    // storage (which is pretty hard to imagine they would have reason
-    // to do).
-
-    uint64_t readIntReg(const StaticInst *si, int idx)
-    {
-        return cpuXC->readIntReg(si->srcRegIdx(idx));
-    }
-
-    FloatReg readFloatReg(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return cpuXC->readFloatReg(reg_idx, width);
-    }
-
-    FloatReg readFloatReg(const StaticInst *si, int idx)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return cpuXC->readFloatReg(reg_idx);
-    }
-
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return cpuXC->readFloatRegBits(reg_idx, width);
-    }
-
-    FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
-    {
-        int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
-        return cpuXC->readFloatRegBits(reg_idx);
-    }
-
-    void setIntReg(const StaticInst *si, int idx, uint64_t val)
-    {
-        cpuXC->setIntReg(si->destRegIdx(idx), val);
-    }
-
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        cpuXC->setFloatReg(reg_idx, val, width);
-    }
-
-    void setFloatReg(const StaticInst *si, int idx, FloatReg val)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        cpuXC->setFloatReg(reg_idx, val);
-    }
-
-    void setFloatRegBits(const StaticInst *si, int idx,
-                         FloatRegBits val, int width)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        cpuXC->setFloatRegBits(reg_idx, val, width);
-    }
-
-    void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
-    {
-        int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
-        cpuXC->setFloatRegBits(reg_idx, val);
-    }
-
-    uint64_t readPC() { return cpuXC->readPC(); }
-    uint64_t readNextPC() { return cpuXC->readNextPC(); }
-    uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
-
-    void setPC(uint64_t val) { cpuXC->setPC(val); }
-    void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
-    void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
-
-    MiscReg readMiscReg(int misc_reg)
-    {
-        return cpuXC->readMiscReg(misc_reg);
-    }
-
-    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
-    {
-        return cpuXC->readMiscRegWithEffect(misc_reg, fault);
-    }
-
-    Fault setMiscReg(int misc_reg, const MiscReg &val)
-    {
-        return cpuXC->setMiscReg(misc_reg, val);
-    }
-
-    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
-    {
-        return cpuXC->setMiscRegWithEffect(misc_reg, val);
-    }
-
-#if FULL_SYSTEM
-    Fault hwrei() { return cpuXC->hwrei(); }
-    int readIntrFlag() { return cpuXC->readIntrFlag(); }
-    void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
-    bool inPalMode() { return cpuXC->inPalMode(); }
-    void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
-    bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
-#else
-    void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
-#endif
-
-    bool misspeculating() { return cpuXC->misspeculating(); }
-    ExecContext *xcBase() { return xcProxy; }
-};
-
-#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__