Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/clean/m5-clean

arch/alpha/ev5.cc:
cpu/o3/regfile.hh:
    Hand merge.

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
extra : convert_revision : c941dd2198851398820b38a66471372ed8454891

1 files changed, 19 insertions, 6 deletions

diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index c58b3c5ba..243172821 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -65,6 +65,7 @@ class SimpleCPU : public BaseCPU
 {
   protected:
     typedef TheISA::MachInst MachInst;
+    typedef TheISA::MiscReg MiscReg;
   public:
     // main simulation loop (one cycle)
     void tick();
@@ -321,15 +322,27 @@ class SimpleCPU : public BaseCPU
     uint64_t readPC() { return xc->readPC(); }
     void setNextPC(uint64_t val) { xc->setNextPC(val); }
 
-    uint64_t readUniq() { return xc->readUniq(); }
-    void setUniq(uint64_t val) { xc->setUniq(val); }
+    MiscReg readMiscReg(int misc_reg)
+    {
+        return xc->readMiscReg(misc_reg);
+    }
+
+    MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+    {
+        return xc->readMiscRegWithEffect(misc_reg, fault);
+    }
 
-    uint64_t readFpcr() { return xc->readFpcr(); }
-    void setFpcr(uint64_t val) { xc->setFpcr(val); }
+    Fault setMiscReg(int misc_reg, const MiscReg &val)
+    {
+        return xc->setMiscReg(misc_reg, val);
+    }
+
+    Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+    {
+        return xc->setMiscRegWithEffect(misc_reg, val);
+    }
 
 #if FULL_SYSTEM
-    uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
-    Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
     Fault hwrei() { return xc->hwrei(); }
     int readIntrFlag() { return xc->readIntrFlag(); }
     void setIntrFlag(int val) { xc->setIntrFlag(val); }