summaryrefslogtreecommitdiff
path: root/cpu/simple/cpu.hh
diff options
context:
space:
mode:
authorAli Saidi <saidi@eecs.umich.edu>2006-03-26 21:44:22 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-26 21:44:22 -0500
commitc27c122afc6b778e67a9c77915fac71730a5a4ef (patch)
tree3056d2ebc1c9eb74fc8d850a942666ce46ad2026 /cpu/simple/cpu.hh
parent4973a16b34471dcb5f65a1d6c31d5a7d8c2dfd83 (diff)
downloadgem5-c27c122afc6b778e67a9c77915fac71730a5a4ef.tar.xz
Add the bus and connector objects to scons
change getPort parameter from char* to string Add an extra phase between construction and init called connect SConscript: Add the bus and connector objects to scons cpu/simple/cpu.cc: cpu/simple/cpu.hh: the connection to memory shouldn't be made until we know the memory object exists (e.g. after construction) dev/io_device.hh: change to const string mem/bus.hh: change getPort parameter from char* to string initialize num_interfaces mem/mem_object.hh: change getPort parameter from char* to string mem/physical.cc: mem/physical.hh: change getPort parameter from char* to string get rid of the bus object I created last time python/m5/objects/PhysicalMemory.py: get rid of the bus object I created last time sim/main.cc: sim/sim_object.cc: sim/sim_object.hh: Add an extra phase between construction and init called connect --HG-- extra : convert_revision : 0e994f93374fa72a06d291655c440ff1b8e155a9
Diffstat (limited to 'cpu/simple/cpu.hh')
-rw-r--r--cpu/simple/cpu.hh1
1 files changed, 1 insertions, 0 deletions
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index dc07027f9..43287a33b 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -105,6 +105,7 @@ class SimpleCPU : public BaseCPU
virtual Packet *recvRetry();
};
+ MemObject *mem;
CpuPort icachePort;
CpuPort dcachePort;