Replace Memory with MemObject; no need for two different levels of hierarchy there.

Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f

1 files changed, 2 insertions, 3 deletions

diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 21944a49f..ed464c605 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -46,7 +46,7 @@
 class Processor;
 class AlphaITB;
 class AlphaDTB;
-class Memory;
+class MemObject;
 
 class RemoteGDB;
 class GDBListener;
@@ -58,7 +58,6 @@ class Process;
 #endif // FULL_SYSTEM
 
 class ExecContext;
-class MemInterface;
 class Checkpoint;
 
 namespace Trace {
@@ -180,7 +179,7 @@ class SimpleCPU : public BaseCPU
         AlphaITB *itb;
         AlphaDTB *dtb;
 #else
-        Memory *mem;
+        MemObject *mem;
         Process *process;
 #endif
     };